20.5.3.4 Detecting Bus Collisions and Resending Messages

When a bus collision occurs, the host module sets the BCL status bit and generates an error (I2CxEIF) interrupt if the BCLDIE (I2CxINTC[15]) bit is enabled. If a bus collision occurs during a byte transmission, the transmission is stopped, the TBF status bit is cleared, and the SDAx and SCLx pins are deasserted. If a bus collision occurs during a Start, Repeated Start, Stop or Acknowledge condition, the condition is aborted, the respective control bits in the I2CxCON register are cleared, and the SDAx and SCLx lines are deasserted.

If the user software is expecting an interrupt at the completion of the host event, the user software can check the BCL status bit to determine if the host event completed successfully or a bus collision occurred (or it may branch to a bus collision interrupt on bus collision), or a host interrupt occurred in case of a successful host event. If a bus collision occurs, the user software must abort sending the rest of the pending message and prepare to resend the entire message sequence, beginning with the Start condition, after the bus returns to the Idle state. The user software can monitor the S and P status bits to wait for an Idle bus. When the user software executes the host Interrupt Service Routine (ISR) and the I²C bus is free, the user software can resume communication by asserting a Start condition.