8.2.6 Protection Region x End Address Offset Register

Note:
  1. Register is read-only unless RTYPE[1:0] bits are ‘11’ and LOCK[1:0] bits (PRLOCK[1:0]) are ‘11’. Firmware configurable region descriptors are locked (read-only) at Reset and must be unlocked with a write to PRLOCK before being modified.
  2. End address offset is a last byte offset from the beginning of the user program Flash (0x800000 address).
  3. END value is loaded from Configuration Words. For example, to configure the end address as 0x812FFF, the END value can be 0x12FFF.
Table 8-6. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: PRxEND
Offset: 0x308, 0x318, 0x328, 0x338, 0x348, 0x358, 0x368, 0x378

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  END[22:16] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxx000 
Bit 15141312111098 
 END[15:12]END[11:8] 
Access R/WR/WR/WR/WRRRR 
Reset xxxx1111 
Bit 76543210 
 END[7:0] 
Access RRRRRRRR 
Reset 11111111 

Bits 22:16 – END[22:16]  Most Significant bits of the Protection Region Last Byte Address Offset(1,2,3)

Bits 15:12 – END[15:12]  Most Significant bits of the Protection Region Last Byte Address Offset(1,2)

Bits 11:8 – END[11:8] Least Significant bits of the Protection Region Last Byte Address Offset. Fixed value 0xFFF.

Bits 7:0 – END[7:0] Least Significant bits of the Protection Region Last Byte Address Offset. Fixed value 0xFFF.