8.2.5 Protection Region x Start Address Offset Register

Note:
  1. Register is read-only unless RTYPE[1:0] bits are ‘11’ and LOCK[1:0] bits (PRLOCK[1:0]) are ‘11’. Firmware configurable region descriptors are locked (read-only) at Reset and must be unlocked with a write to PRLOCK before being modified.
  2. Start address offset is a first byte offset from the beginning of the user program Flash (0x800000 address).
  3. Start address value is loaded from Configuration Words. For example, to configure the start address as 0x812000, the START value can be 0x12000.
Table 8-5. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: PRxST
Offset: 0x304, 0x314, 0x324, 0x334, 0x344, 0x354, 0x364, 0x374

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  START[22:16] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxx000 
Bit 15141312111098 
 START[15:12]START[11:8] 
Access R/WR/WR/WR/WRRRR 
Reset xxxx0000 
Bit 76543210 
 START[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 22:16 – START[22:16]  Most Significant bits of the Protection Region First Byte Address Offset(1,2)

Bits 15:12 – START[15:12]  Most Significant bits of the Protection Region First Byte Address Offset(1,2)

Bits 11:8 – START[11:8] Least Significant bits of the Protection Region First Byte Address Offset. Fixed value 0x000.

Bits 7:0 – START[7:0] Least Significant bits of the Protection Region First Byte Address Offset. Fixed value 0x000.