18.3.5 UARTx Transmit Buffer Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | UxTXB |
| Offset: | 0x1710, 0x1750, 0x1790 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LAST | |||||||||
| Access | W | ||||||||
| Reset | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXB[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | x | x | x | x | x | x | x | x | |
Bit 15 – LAST Last Byte Indicator for Smart Card Support bit
Bits 7:0 – TXB[7:0] Transmitted Character Data bits 7-0
If the buffer is full, further writes to the buffer are ignored.