18.3.7 UARTx Timing Parameter B Register
Note:
- The WIP bit is relevant when the UART clock differs from the CPU clock. This bit indicates whether the UART and CPU clocks are synchronized for writes to the parameter registers.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | UxPB |
| Offset: | 0x1718, 0x1758, 0x1798 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WIP | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| P3[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| P3[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| P3[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – WIP UxPB Write in Progress bit(1)
| Value | Description |
|---|---|
1 | Write still in progress (user should not update the UxPB registers) |
0 | No write in progress (user can update the UxPB registers) |
Bits 23:0 – P3[23:0] Parameter 3 bits
DMX RX:
The last byte number to receive – 1, not including start code (bits[8:0]).
LIN Responder RX:
Number of bytes to receive (bits[7:0]).
Asynchronous RX:
Used to mask the P2 address bits; 1 = P2 address bit is used, 0 = P2 address bit is masked off (bits[7:0]).
Smart Card Mode:
Waiting Time Counter bits (bits[23:0]).
Other Modes:
Not used.