13.5.2 Standard Operation (Data Transfer)

A basic example of using the DMA Controller is moving a constant stream of data from a serial communication channel, such as a UART, and buffering it in a location in data RAM until the CPU can process it. In this example, DMA channel 0 is used to service the UART for 16 data transfers in one iteration. It is configured as follows:

• DMA channel 0 is configured to use the UART’s receive interrupt as a trigger.
• DMA channel 0 is programmed to use a single source address; to auto-increment the destination address with destination address reload enabled. and to use Repeated One-Shot Data Transfer mode.
• DMA0SRC is programmed with the address of the UART’s receive buffer; DMA0DST is programmed with an address in data RAM.
• To support 16 transfers in one iteration, DMA0CNT is programmed with 0015h.

In this configuration, the sequence of events is as follows:

1. When the UART triggers a receive interrupt, DMA0 transfers the data from the buffer to a data RAM location.
2. After the transfer, the destination address is incremented.
3. After 16 interrupts, DMA0CNT is decremented to 0000h. Because this is a Repeated mode transfer, the original values of DMA0CNT is reloaded and the cycle repeats. The value of DMA0DEST is also reloaded as RELOADD is enabled.

This process allows the CPU to perform different tasks other than buffering incoming serial data and processes the data when it has the time. Because the DMA is overwriting the same 16 locations in memory, it is assumed that the CPU will be able to retrieve the fresh data first.