13.5.3 Nested Operation (Wait State Generation)

DMA channels may be nested, using one channel to trigger another in performing a data transfer. When one of the microcontroller’s general purpose timers is included, it becomes possible to generate a fixed delay between a service request and the data transfer. In this case, DMA0 and DMA1 are used to service a UART after a forced Wait state. DMA channels 0 and 1 are preconfigured as follows:

  • DMA channel 0 is configured to use the UART’s receive interrupt as a trigger.
  • DMA0SRC is programmed with an address in data RAM; DMA0DST is programmed with the address of the T0CON register.
  • DMA channel 1 is configured to use Timer0’s interrupt as a trigger.
  • DMA1SRC is programmed with the address of the UART’s receive buffer; DMA0DST is programmed for the address of a destination in data RAM.

The sequence of events is as follows:

  1. When the UART sends an interrupt, DMA0 transfers data into Timer0’s Control register.
  2. This causes Timer0 to count down once for a fixed interval (the Wait state), then generates an interrupt.
  3. When Timer0 sends its interrupt, DMA1 is triggered and transfers data from the UART to data RAM.
  4. Note that in this case, neither DMA channel was servicing the module from which it received its trigger.