13.5.4 Cascaded Operation (SPI Duplex Servicing)

Another method is to cascade two DMA channels together, allowing one to perform part of a function and then trigger a second channel to perform the other part. A good example is an SPI module operating in Client mode. Using two cascaded DMA channels allows automatic duplex operation, alternately receiving and sending data without the CPU’s intervention. DMA0 (the read channel) and DMA1 (the write channel) are configured as follows:

  • DMA0 is configured to use the SPI’s transfer interrupt as the trigger for Repeated One-Shot transfers, with a fixed source address and a fixed destination address.
  • DMA0SRC is programmed with the address of SPIBUF, while DMA0DST is programmed with a destination address in data RAM.
  • DMA0CNT is programmed with 0001h (its default).
  • DMA1 is configured to use the DMA0 interrupt as the trigger for Repeated One-Shot transfers and for fixed source and destination addresses.
  • DMA1SRC is programmed with a data source address in data RAM, while DMA1DST is programmed with the address of SPIBUF.
  • DMA1CNT is programmed with 0001h.

The sequence of events is as follows:

  1. When the SPI receives data, it causes an SPI transfer interrupt.
  2. This triggers DMA0 to transfer the data from the SPI buffer into RAM. At the completion of the transfer, the DMA0 interrupt is triggered.
  3. The DMA0 interrupt triggers DMA1 to move data out of the data RAM location into SPIBUF to be transmitted. The process ends at this point.

For simplicity, this example moves one word of data in and out of the SPI. By changing the SAMODEx and DAMODEx bits for DMA0 and DMA1, respectively, and using different values for DMAxCNT, it is also possible to create multiword buffers for larger duplex transactions.