Register bits are read-only
in Receive mode (RCVEN = 1).
In Transmit mode, the CRC[3:0] bits are read-only when automatic CRC
calculation is enabled (RCVEN = 0, CRCEN =
1).
Table 21-7. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
SENTxDAT
Offset:
0x0019D4,
0x0019F4
Bit
31
30
29
28
27
26
25
24
STAT[3:0]
DATA1[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA2[3:0]
DATA3[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DATA4[3:0]
DATA5[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA6[3:0]
CRC[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:28 – STAT[3:0]
Status Nibble Data bits(1)
Bits 27:24 – DATA1[3:0]
Data Nibble #1 Data bits(1)
Bits 23:20 – DATA2[3:0]
Data Nibble #2 Data bits(1)
Bits 19:16 – DATA3[3:0]
Data Nibble #3 Data bits(1)
Bits 15:12 – DATA4[3:0]
Data Nibble #4 Data bits(1)
Bits 11:8 – DATA5[3:0]
Data Nibble #5 Data bits(1)
Bits 7:4 – DATA6[3:0]
Data Nibble #6 Data bits(1)
Bits 3:0 – CRC[3:0]
CRC Nibble Data bits(1,2)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
