21.3.1 SENTx Control Register 1
Note:
- These bits have no function when RCVEN =
1. - This bit has no function when RCVEN =
0. - CCP3 OC output is internally connected with SENT1OUT pin, and CCP4 OC output is internally connected with SENT2OUT pin.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | SENTxCON1 |
| Offset: | 0x0019C0, 0x0019E0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | RCVEN | TXM | TXPOL | CRCEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PPP | SPCEN | PS | NIBCNT[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | |||
Bit 15 – ON SENTx Enable bit
| Value | Description |
|---|---|
1 | Module is enabled |
0 | Module is disabled |
Bit 13 – SIDL SENTx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 | Module stops operation in Idle mode |
0 | Module continues operation in Idle mode |
Bit 11 – RCVEN SENTx Receive Enable bit
| Value | Description |
|---|---|
1 | Module operates as a receiver |
0 | Module operates as a transmitter |
Bit 10 – TXM SENTx Transmit Mode bit(1)
| Value | Description |
|---|---|
1 | Module transmits data frame only when triggered using the SYNCTXEN status bit |
0 | Module transmits data frame continuously while enabled |
Bit 9 – TXPOL SENTx Transmit Polarity bit(1)
| Value | Description |
|---|---|
1 | Idle state of data output pin is low |
0 | Idle state of data output pin is high |
Bit 8 – CRCEN CRC Enable bit
In Receive Mode (RCVEN = 1):
1 = CRC verification is performed using the J2716 method
0 = CRC verification is not performed
In Transmit Mode (RCVEN = 0):
1 = CRC is calculated using the J2716 method
0 = CRC is not calculated
Bit 7 – PPP Pause Pulse Present bit
| Value | Description |
|---|---|
1 | SENTx messages transmitted/received with Pause pulse |
0 | SENTx messages transmitted/received without Pause pulse |
Bit 6 – SPCEN Short PWM Code Enable bit(2,3)
| Value | Description |
|---|---|
1 | SPC control from external source is enabled |
0 | SPC control from external source is disabled |
Bit 4 – PS Prescale Select bit
| Value | Description |
|---|---|
1 | 1:4 (module clock is FSENT/4) |
0 | 1:1 (module clock is FSENT) |
Bits 2:0 – NIBCNT[2:0] Nibble Count Control bits
| Value | Description |
|---|---|
111 | Reserved: do not use |
110 | Six data nibbles per data packet |
101 | Five data nibbles per data packet |
100 | Four data nibbles per data packet |
011 | Three data nibbles per data packet |
010 | Two data nibbles per data packet |
001 | One data nibble per data packet |
000 | Reserved: do not use |