13.3.5 DMA Channel x Control Register

Note:

The number of transfers per CHREQ bit setting depends on TRMODE[1:0].
The channel will only be able to transfer if PCHEN is high, provided that PPEN is also set high for ping-pong operation support.
DMAxCNT register is reloaded in every repeated mode operation regardless of the RELOADC bit state.

Table 13-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DMAxCH
Offset:	0x2310, 0x233C, 0x2368, 0x2394, 0x23C0, 0x23EC


Bit	31	30	29	28	27	26	25	24
			PPEN	PCHEN		RELOADC	RELOADD	RELOADS
Access			R/W	R/W/HS/HC		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
								RETEN
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	SAMODE[1:0]		DAMODE[1:0]		TRMODE[1:0]		FLWCON[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SIZE[1:0]			CHREQ	DONEEN	MATCHEN	HALFEN	CHEN
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W/HC
Reset	0	0		0	0	0	0	0

Bit 29 – PPEN Ping-Pong Operation Enable bit

Value	Description
1	Ping-pong operation support is enabled
0	Ping-pong operation support is disabled

Bit 28 – PCHEN Ping-Pong Channel Enable bit

Intended to support the ping-pong operation; the bit takes effect only when PPEN is set high as follows.

Value	Description
1	The DMA channel is enabled if CHEN is set high; this bit is hardware settable via PCHEN of the other DMA channel pair used in the Ping-Pong mode
0	The DMA channel is disabled

Bit 26 – RELOADC Count Reload bit⁽³⁾

Value	Description
1	DMAxCNT register is reloaded to previous written value (buffered original content) upon the start of the next operation
0	DMAxCNT register is not reloaded

Bit 25 – RELOADD Destination Address Reload bit

Value	Description
1	DMAxDST register is reloaded to previous written value upon the start of the next operation
0	DMAxDST register is not reloaded

Bit 24 – RELOADS Source Address Reload bit

Value	Description
1	DMAxSRC register is reloaded to previous written value upon the start of the next operation
0	DMAxSRC register is not reloaded

Bit 16 – RETEN Read Error Trap Enable bit

Value	Description
1	DMA channel suspends transfer operation on bus read error and asserts DMA trap signal
0	DMA channel continues transfer operation when bus read error is encountered

Bits 15:14 – SAMODE[1:0] Source Address Mode Selection bits

Value	Description
11	Reserved
10	DMAxSRC register is decremented based on SIZE[1:0] after a transfer completion
01	DMAxSRC register is incremented based on SIZE[1:0] after a transfer completion
00	DMAxSRC register remains unchanged after a transfer completion

Bits 13:12 – DAMODE[1:0] Destination Address Mode Selection bits

Value	Description
11	Reserved
10	DMAxDST register is decremented based on SIZE[1:0] after a transfer completion
01	DMAxDST register is incremented based on SIZE[1:0] after a transfer completion
00	DMAxDST register remains unchanged after a transfer completion

Bits 11:10 – TRMODE[1:0] Transfer Mode Selection bits

Value	Description
11	Repeated Continuous
10	Continuous
01	Repeated One-Shot
00	One-Shot

Bits 9:8 – FLWCON[1:0] Data Flow Control bits

Value	Description
11	Reserved
10	Read from DMAxSRC only
01	Read from DMAxSRC followed by write to DMAxDST and DMAxSRC (Null Write mode)
00	Read from DMAxSRC followed by write to DMAxDST

Bits 7:6 – SIZE[1:0] Data Size Selection bits

Value	Description
11	Reserved
10	32-bit word is transferred at a time
01	16-bit word is transferred at a time
00	One byte is transferred at a time

Bit 4 – CHREQ DMA Channel Software Request bit⁽¹⁾

Value	Description
1	A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0	No DMA request is initiated by software

Bit 3 – DONEEN Done Interrupt Enable bit

Value	Description
1	An interrupt is invoked upon DONE flag being set
0	An interrupt is not invoked by DONE condition

Bit 2 – MATCHEN Pattern Match Enable bit

Value	Description
1	Pattern match is enabled
0	Pattern match is disabled

Bit 1 – HALFEN Halfway Completion Watermark bit

Value	Description
1	An interrupt is invoked when the DMAxCNT register value has reached its halfway point
0	An interrupt is not invoked by a half condition

Bit 0 – CHEN DMA Channel Enable bit ⁽²⁾

Value	Description
1	The corresponding DMA channel is enabled
0	The corresponding DMA channel is disabled

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