32.2.4 Peripheral Module Disable 3 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PMD3 |
| Offset: | 0x3A4C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADC2MD | ADC1MD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPAMPMD | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BISS1MD | QEI1MD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 17 – ADC2MD ADC 2 Module Disable bit
| Value | Description |
|---|---|
| 1 | ADC 2 module is disabled |
| 0 | ADC 2 module is enabled |
Bit 16 – ADC1MD ADC 1 Module Disable bit
| Value | Description |
|---|---|
| 1 | ADC 1 module is disabled |
| 0 | ADC 1 module is enabled |
Bit 8 – OPAMPMD Op Amp 1 Module Disable bit
| Value | Description |
|---|---|
| 1 | OPA1 module is disabled |
| 0 | OPA1 module is enabled |
Bit 4 – BISS1MD BiSS 1 Module Disable bit
| Value | Description |
|---|---|
| 1 |
BiSS 1 module is disabled |
| 0 |
BiSS 1 module is enabled |
Bit 0 – QEI1MD QEI 1 Module Disable bit
| Value | Description |
|---|---|
| 1 |
QEI 1 module is disabled |
| 0 |
QEI 1 module is enabled |