4.4.4 Debug RAM

The BMX supports a RAM target for use in Debug mode only. The debug RAM space is at a fixed location and is from 0x7BFE00 to 0x7BFFFF.

The ICD initiator can always access debug RAM. For other initiators, both read and write access to debug scratch pad RAM is disallowed unless the device is in Debug mode. Access to the debug RAM when outside of Debug mode will generate a bus error and set the ADDRERR (BMXxERR[1]) bit. Additionally, debug RAM is not a valid target for the CPU instruction bus regardless of the Debug state and will cause a bus error.

Note that because the CPU does not handle traps while in Debug mode, in some circumstances, bus errors caused in Debug mode may result in a ‘soft lock’ situation that will require a device Reset to resolve.