4.4.5 Bus Error

The BMX generates a bus error exception back to an initiator on any failed access. Failed accesses can occur for a number of reasons:
  • Unimplemented memory in a valid target space. For example, the DMA accessing XRAM higher than allowed by RAM array size.
  • Any location in an invalid target space. For example, ICD addressing Program Space.
  • Instruction bus reads outside of the memory range defined by either of the BMXIRAML/H registers. Note, the BMX will not generate bus errors for instruction bus accesses targeting Flash. The Flash controller will generate the bus error and indicate status in NVMCON register.
  • Instruction bus reads of debug RAM target, regardless of the BMXIRAML/H setting.
  • A RAM write request is generated to the instruction RAM space defined by the BMXIRAML/H registers.
  • Flash or RAM read results in an ECC Double-Bit Error (ECC DED). This bus error is generated by the target and passed up to the initiator, which will cause the initiator's bus error trap.
  • Target indicates a bus error (root causes are target-specific).

When a bus error is generated within the BMX, it will set the relevant bit within the BMXxERR register for the initiator which generated the transaction. The user can diagnose the error by examining the error register of the initiator responsible for the trap, using BMXERRx in conjunction with the target error registers. See Table 4-13 for initiator indexes.

As the BMX supports simultaneous read and write operations to some targets, bus errors are split into separate read or write operation errors. This ensures that even if two simultaneous errors occur, they can both be captured.

Table 4-13. Target to Bus Error Index Mapping
TGTRERRy (BMXxERR[13:8])Target
0Program space read
1Bus splitter/SFRs
2XRAM
3YRAM
4Debug RAM target