12.4.9 Power-Saving Mode

Oscillator module supports multiple Sleep and Idle modes for power reduction:

For clock generator 1
  • Idle mode - System clock stops, peripheral clock, peripheral clock divided run
  • Sleep mode - System clock, peripheral clock, peripheral clock divided stop
Other clock and PLL generators
  • Stop in Idle - CLKGEN/PLL(x) stop in Idle
  • Run in Sleep - CLKGEN/PLL(x) run in Sleep

The Stop in Idle (SIDL) and Run In Sleep (RIS) options are user selectable via the SIDLE and RIS bits in the CLKxCON/PLLCONx registers.

If the SIDLE bit is set in a CLKxCON/PLLCONx register, the associated clock will stop if CPU IDLE is asserted. The SIDLE bit has no effect if CPU Sleep is asserted.

If the RIS bit is set in a CLKxCON/PLLCONx register, the associated clock will continue to run even if CPU Sleep is asserted. The RIS bit has no effect if CPU Idle is asserted.

Clock generator 1 is the clock source for the system clock (sys_clk) and peripheral clock. The PWRSAV instruction that initiates Idle and Sleep mode is primarily responsible for reducing processor and system power consumption.

In Sleep and Idle mode, the processor clock, system and fast peripheral clock, and peripheral clock are all disabled