12.4.2 Phase-Locked Loop (PLL)

The POSC and Internal FRC Oscillator sources can optionally use an on-chip PLL to obtain higher operating speeds. Figure 12-8 illustrates a block diagram of the PLL module.

Figure 12-8. PLL Block Diagram

For PLL operation, the frequency range requirements as specified in Electrical Characteristics, must be met at all times without exception for the following frequencies:

  • PLL Input Frequency (FPLLI)
  • VCO Frequency
  • Feedback Divider
  • Output of the PLL module . The first output divider (POSTDIV1) value should be larger than the value for the second output divider (POSTDIV2).

The PLL Phase Detector Input Divider Select bits (PLLPRE[3:0]) in the PLL Divider register (PLLxDIV[29:24]) specify the input divider ratio (N1), which is used to scale down the input clock (FPLLI) to meet the PFD input frequency range.

The PLL Feedback Divider bits (PLLFBDIV[7:0]) in the PLL Divider register (PLLFBD[7:0]) specify the divider ratio (M), which scales down the VCO Output Frequency (FVCO) for feedback to the PFD input. The VCO Frequency (FVCO) is ‘M’ times the PFD Input Frequency (FPFD).

There are two PLL VCO output dividers configured through the POSTDIV1[2:0] and POSTDIV2[2:0] select bits. These bits are located in the PLL Divider register (PLLxDIV[6:4] and PLLxDIV[2:0]) and specify the divider ratios (N2 and N3) that limit the PLL Output Frequency (PLL FOUT). Please refer to Table 12-2 for max frequencies related to each peripheral.

Equation 12-2 provides the relationship between the PLL Input Frequency (FPLLI) and VCO Output Frequency (FVCO).

Equation 12-2. FVCO Calculation

Equation 12-3 provides the relationship between the PLL Input Frequency (FPLLI) and PLL Output Frequency (FPLLO).

Equation 12-3. FPLLO Calculation