3.4.3.1 Cache/ISB Manual Invalidation

Manual invalidation of the Instruction Cache and ISBs is used to force cache coherency when the user knows that the cache and Flash contents may not match. It occurs under the following conditions:

  • CHECON.CHEINV Control bit: When set by software, this bit will invalidate both the Instruction Cache and all ISBs. This bit will clear automatically by hardware after the cache and ISB memory have been invalidated.
    Note: CHECON.CHEINV is also cleared should an automatic invalidation occur after the bit has been set.
  • CHECON.ON control bit: The Instruction Cache memory and ISB buffers are invalidated when the CHECON.ON bit is cleared. This will be the case out of Reset. Execution continues using only a single default ISB slice. Setting CHECON.ON has no effect with respect to cache/ISB invalidation as it is already invalidated and the active ISB will contain valid data from the current instruction flow.