40.13.8 Host Interrupt Pipe Set Register
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Name: | PINTENSETn |
Offset: | 0x0109 + n*0x20 [n=0..7] |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
STALL | TXSTP | PERR | TRFAIL | TRCPT1 | TRCPT0 | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 2 |
Bit 5 – STALL Stall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value | Description |
---|---|
0 | The Stall interrupt is disabled. |
1 | The Stall interrupt is enabled. |
Bit 4 – TXSTP Transmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value | Description |
---|---|
0 | The Transmitted Setup interrupt is disabled. |
1 | The Transmitted Setup interrupt is enabled. |
Bit 3 – PERR Pipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value | Description |
---|---|
0 | The Pipe Error interrupt is disabled. |
1 | The Pipe Error interrupt is enabled. |
Bit 2 – TRFAIL Transfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value | Description |
---|---|
0 | The Transfer Fail interrupt is disabled. |
1 | The Transfer Fail interrupt is enabled. |
Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x.
0.2.7 Host Registers - Pipe RAM
Value | Description |
---|---|
0 | The Transfer Complete x interrupt is disabled. |
1 | The Transfer Complete x interrupt is enabled. |