4.7.2 FEEN1 – RF Front-end Enable Register 1
| Name: | FEEN1 |
| Offset: | 0x101 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | PLSP1 | ADCLK | ADEN | LNAEN | XTOEN | PLCAL | PLEN | |
| Access | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 6 – PLSP1 PLL Speed-Up
If this bit is written to ‘1’, the fractional-N PLL speed-up mode is activated. This bit must be set to ‘0’ after the FESR.PLCK is locked.
Bit 5 – ADCLK ADC Clock Enable
If this bit is written to ‘1’, the ADC clock is activated. It has to be set > 50 μs after ADEN is set because the internal biasing of the ADC must settle before the clock is activated.
Bit 4 – ADEN Analog Digital Converter Enable
If this bit is written to ‘1’, the DC biasing of the ADC is activated.
Bit 3 – LNAEN Low Noise Amplifier Enable
If this bit is written to ‘1’, either the Low-band or the High-band LNA is enabled. The FECR.LBNHB bit controls which LNA is activated.
Bit 2 – XTOEN Crystal Oscillator Enable
If this bit is written to ‘1’, the crystal oscillator is started. This bit enables the XTO, which operates in IDLEMode(XTO), RXMode. The XTO frequency is available as soon as FESR.XRDY is set by the XTO.
Bit 1 – PLCAL PLL Calibration Mode
If this bit is written to ‘1’, the PLL is set to calibration mode. In this mode, the loop filter is clamped to nominal control voltage AVCC/2 and the charge pump is deactivated. During the calibration mode, the frequency is measured with a counter and the correct FEVCT.FEVCT[3:0] frequency setting for the VCO is determined by the sequencer state machine.
Bit 0 – PLEN PLL Enable
If this bit is written to ‘1’, the fractional-N PLL is activated.
