4.7.1 FESR – RF Front-End Status Register

Name: FESR
Offset: 0x100
Reset: 0x00

Bit 76543210 
 PLCKXRDYHBSATLBSAT 
Access RRRRRRRR 
Reset 00000000 

Bit 7 –  Reserved Bit

This bit is reserved and read as ‘0’.

Bit 6 –  Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 –  Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 –  Reserved Bit

This bit is reserved and read as ‘0’.

Bit 3 – PLCK PLL Locked

This status bit is set to ‘1’ if the PLL is locked within the time window specified by FECR.PLCKG. It shows that a stable frequency is available from the fractional-N PLL.

Bit 2 – XRDY XTO Ready

This status bit is set to ‘1’ if the XTO amplitude is settled and provides a reliable clock output. If this bit is set to ‘1’, the XTO frequency is available to the AVR and the fractional-N PLL.

Bit 1 – HBSAT LNA High-Band Saturated

This status bit is set to ‘1’ if the RF input level at RFIN_HB exceeds -39 dBm and if FECR.HBNLB = 1.

Bit 0 – LBSAT LNA Low-Band Saturated

This status bit is set to ‘1’ if the RF input level at RFIN_LB exceeds -39 dBm and if FECR.HBNLB = 0. Depending on FECR.HBNLB, one of the two HBSAT and LBSAT bits is always set to ‘1’ if the RF input level exceeds -39 dBm For more details, refer to the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E), section 4.5, parameter number 8.60. In order to cope with higher RF levels, the FECR.ANDP register bit can be set which attenuates the input power by 15 dB for the Low-band or 18 dB for the High-band. For more details, refer to the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E), section 4.5, parameter number 8.80.