4.7.9 FECR – RF Front-End Control Register
| Name: | FECR |
| Offset: | 0x10A |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | ANPS | PLCKG | ADHS | ANDP | S4N3 | LBNHB | |
| Access | R | R | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 5 – ANPS ASK Not DPSK Switch
This bit must always be set to ‘1’.
Bit 4 – PLCKG PLL Lock Detect Gate
Setting this bit to ‘1’ opens a time window during which the fractional-N PLL detects frequency locking. If the PLL frequency is close to the wanted frequency, the status bit FESR.PLCK is set to ‘1’.
Bit 3 – ADHS ADC High Sample Rate
This bit must be set to ‘1’ if the ADC is used with a high sample rate.
Bit 2 – ANDP Antenna Damping
If this bit is written to
‘1’, the damping in the SPDT RF switch is activated. Antenna
damping must be activated if the status bit FESR.HBSAT (High-band) or FESR.LBSAT
(Low-band) is set to ‘1’. This bit is controlled by the sequencer
state machine if it is not disabled in SSMRCR.SSMADA/B. See Get Telegram State
Machine from Related Links.
Bit 1 – S4N3 Select 433 MHz Not 315 MHz Band
If this bit is written to ‘1’, in Low-band (LBNHB = 1), select the 418-477 MHz band. Otherwise, select the 310-318 MHz band. If High-band is activated (LBNHB = 0), this bit must be set to ‘0’.
Bit 0 – LBNHB Select Low-band Not High-band
If this bit is written to ‘1’, Low-band is selected. Otherwise, High-band is used. This influences the LNA, the mixers and the fractional-N PLL.
