3.11.12.2 Channel-Specific Configuration

This section contains the channel-specific part of a service configuration.

Note: The addresses shown are for service 0/channel 0. For more details on the addresses for different services and channels, see EEPROM Map from Related Links.

FFREQ[2:0]

The FFREQ[2:0] variables are a copy of the fractional frequency registers (FFREQ[2:1]L/M/H) and contain the base frequency setting for the fractional-N PLL. For more details on the functional description, see Demodulation Settings from Related Links. For more details on the hardware description, see Fractional-N PLL from Related Links.

Address

Ser0/Ch0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0139

FFREQ[0]

FFREQL[7:0]

0x013A

FFREQ[1]

FFREQM[7:0]

0x013B

FFREQ[2]

FFREQH[7:0]

Bits 7..0: FFREQL/M/H – Fractional Frequency Base Setting

FEMS

The FEMS variable is a copy of the RF Front End Main and Swallow control register (FEMS) and contains the main and swallow counter values of the fractional-N PLL. For more details on the functional description, see Demodulation Settings from Related Links. For more details on the hardware description, see Fractional-N PLL from Related Links.

Address

Ser0/Ch0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x013C

FEMS

PLLM[3:0]

PLLS[3:0]

Bits 7..4: PLLM[3:0] – PLL M Counter Divider Ratio

Bits 3..0: PLLS[3:0] – PLL S Counter Divider Ratio

FECR

The FECR variable is a copy of the RF Front End Control Register (FECR) and contains control settings of the fractional-N PLL. For more details on the functional description, see Demodulation Settings from Related Links. For more details on the hardware description, see Fractional-N PLL from Related Links.

Address

Ser0/Ch0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x013D

FECR

——

ANPS

PLCKG

ADHS

ANDP

S4N3

LBNHB

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: ANPS – ASK not DPSK Switch.

This bit must be set to ‘0’ because the function is controlled by the firmware/SSM.

Bit 4: PLCKG – PLL Lock Detect Gate

This bit must be set to ‘0’ because the function is controlled by the firmware/SSM.

Bit 3: ADHS – ADC High Sample Rate

This bit must be set to ‘0’ because the function is controlled by the firmware/SSM.

Bit 2: ANDP – Antenna Damping

This bit must be set to ‘0’ because the function is controlled by the firmware/SSM.

Bit 1: S4N3 – Select 433 MHz not 315 MHz Band

Bit 0: LBNHB – Select Low-Band not High-Band