3.11.12.1 Service-Specific Configuration

This configuration contains the service-specific part of a service configuration.

Note: The used addresses are for service 0. For more details on the addresses for service 1 and service 2, see EEPROM Map from Related Links.

CHCR

The CHCR variable is a copy of the channel filter configuration register (CHCR) and contains the channel filter configuration settings. For more details on the functional description, see Channel Filter from Related Links. For more details on the hardware description, see RX Digital Signal Processing (RX DSP) from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00BB

CHCR

————

BWM[3:0]

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 3..0: BWM – Bandwidth Mode

CHDN

The CHDN variable is a copy of the channel filter down-sampling register (CHDN) and contains the channel filter down-sampling settings. For more details on the functional description, see Channel Filter from Related Links. For more details on the hardware description, see RX Digital Signal Processing (RX DSP) from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00BC

CHDN

——

ADCDN

BBDN[4:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: ADCDN – ADC Down Sampling Configuration

Bits 4..0: BBDN[4:0] – Baseband Filter Down Sampling Ratio

CHSTARTFILTER

The CHSTARTFILTER variable is a copy of the SSM filter bandwidth register (SSMFBR) and contains the channel filter start-up time settings. For more details on the functional description, see Channel Filter from Related Links. For more details on the hardware description, see Sequencer State Machine from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00BD

CHSTARTFILTER

——

PLDT

HADT

DFDT

FID[2:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: PLDT – PLL Lock Delay Time

Bit 4: HADT – Half Antenna Damping Delay Time

Bit 3: DFDT – Double Filter Delay Time

Bits 2..0: FID – Filter Delay

DMCDA, DMCDB

The DMCDA/B variables are a copy of the demodulator carrier detect registers (DMCDA/B) and contain the demodulator carrier detect settings for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Demodulator and Signal Checks from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00BE

DMCDA

DMCTA[2:0]

DMCLA[4:0]

0x00BF

DMCDB

DMCTB[2:0]

DMCLB[4:0]

Bits 7..5: DMCTA/B[2:0] – Demodulator Carrier Detect Time for Path A/B

Bits 4..0: DMCLA/B[4:0] – Demodulator Carrier Detect Limit for Path A/B

DMCRA, DMCRB

The DMCRA/B variables are a copy of the demodulator control registers (DMCRA/B) and contain the demodulator control settings for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Demodulator and Signal Checks from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C0

DMCRA

DMARA

SY1TA

SASKA

DMPGA[4:0]

0x00C1

DMCRB

DMARB

SY1TB

SASKB

DMPGB[4:0]

Bit 7: DMARA/B – Demodulator Automatic Restart on Path A/B

Bit 6: SY1TA/B – Symbol Check with 1T only on Path A/B

Bit 5: SASKA/B – Select ASK Input for Path A/B

Bits 4..0: DMPGA/B[4:0] – Demodulator PLL Loop Gain for Path A/B

DMDRA, DMDRB

The DMDRA/B variables are a copy of the demodulator data rate registers (DMDRA/B) and contain the demodulator data rate settings for path A and path B. For more details on the functional description, see Demodulation Settings from Related Links. For more details on the hardware description, see Demodulator and Signal Checks from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C2

DMDRA

DMDNA[3:0]

DMAA[3:0]

0x00C3

DMDRB

DMDNB[3:0]

DMAB[3:0]

Bits 7..4: DMDNA/B – Demodulator Down Sampling on Path A/B

Bits 3..0: DMAA/B – Demodulator Moving Average Data Rate Factor on Path A/B

DMMA, DMMB

The DMMA/B variables are a copy of the demodulator mode registers (DMMA/B) and contain the demodulator operating mode settings for path A and path B. For more details on the functional description, see Demodulation Settings from Related Links. For more details on the hardware description, see Demodulator and Signal Checks from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C4

DMMA

DMNEA

DMHA

DMPA

DMATA[4:0]

0x00C5

DMMB

DMNEB

DMHB

DMPB

DMATB[4:0]

Bit 7: DMNEA/B – Demodulator NRZ Enable for Path A/B

Bit 6: DMHA/B – Demodulator Hold Mode for Path A/B

Bit 5: DMPA/B – Demodulator Received Data Polarity for Path A/B

Bits 4..0:DMATA/B[4:0] – Demodulator Amplitude Threshold for Path A/B

EOT1A, EOT1B

The EOT1A/B variables are a copy of the end of telegram conditions 1 registers (EOTC1A/B) and contain the EOT configuration during WUP check for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links. For more details on the hardware description, see RX DSP Control from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C6

EOT1A

EOTBFE

RRFEA

TELREA

TMOFEA

MANFEA

SYTFEA

AMPFEA

CARFEA

0x00C7

EOT1B

EOTAFE

RRFEB

TELREB

TMOFEB

MANFEB

SYTFEB

AMPFEB

CARFEB

Bit 7: EOTB/AFE – End of Telegram on Path B/A Fail Enable

Bit 6: RRFEA/B – RSSI Range Fail Enable on Path A/B

Bit 5: TELREA/B – Telegram Length Reached Enable on Path A/B

Bit 4: TMOFEA/B – Time-out Fail Enable on Path A/B

Bit 3: MANFEA/B – Manchester Coding Fail Enable on Path A/B

Bit 2: SYTFEA/B – Symbol Timing Check Fail Enabled on Path A/B

Bit 1: AMPFEA/B – Demodulation Amplitude Check Fail Enable on Path A/B

Bit 0: CARFA/B – Carrier Check Fail Enable on Path A/B

EOT2A, EOT2B

The EOT2A/B variables are a copy of the end of telegram conditions 2 registers (EOTC2A/B) and contain the EOT configuration during SFID check for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links. For more details on the hardware description, see RX DSP Control from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C8

EOT2A

EOTBFE

RRFEA

TELREA

TMOFEA

MANFEA

SYTFEA

AMPFEA

CARFEA

0x00C9

EOT2B

EOTAFE

RRFEB

TELREB

TMOFEB

MANFEB

SYTFEB

AMPFEB

CARFEB

See EOT1A, EOT1B variables for the bit descriptions.

EOT3A, EOT3B

The EOT3A/B variables are a copy of the end of telegram conditions 3 registers (EOTC3A/B) and contain the EOT configuration during payload reception for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links. For more details on the hardware description, see RX DSP Control from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00CA

EOT3A

EOTBFE

RRFEA

TELREA

TMOFEA

MANFEA

SYTFEA

AMPFEA

CARFEA

0x00CB

EOT3B

EOTAFE

RRFEB

TELREB

TMOFEB

MANFEB

SYTFEB

AMPFEB

CARFEB

See EOT1A, EOT1B variables for the bit descriptions.

FEALR_FEANT

The FEALR_FEANT variable contains the antenna-related settings of the RF front end antenna registers (FEALR and FEANT).

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00CC

FEALR_FEANT

——

FEALR.RNGE[1:0]

FEANT.LVLC[3:0]

FEALR_FEANT is always set to 0x00.

FEVCO

The FEVCO variable is a copy of the RF front end VCO and PLL control register (FEVCO) and contains the front end VCO control settings. For more details on the hardware description, see VCO from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00CF

FEVCO

VCOB[3:0]

CPCC[3:0]

Bits 7..4: VCOB[3:0] – VCO Bias

Bits 3..0: CPCC[3:0] – Charge Pump Current Control

FEVCT

The FEVCT variable is a copy of the RF front end VCO tuning register (FEVCT) and contains VCO tuning control settings. For more details on the functional description, see VCO Tuning from Related Links. For more details on the hardware description, see VCO from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00D0

FEVCT

————

FEVCT[3:0]

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 3..0: FEVCT[3:0] – Front-end VCO Tuning Control Initial value for the VCO tuning. The default value is 7.

FREQoffset

The FREQoffset variable contains the frequency offset for sub-channeling. For more details on the functional description, see Subchanneling from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00D1

FREQoffset[0]

FREQoffset[7:0]

0x00D2

FREQoffset[1]

FREQoffset[15:8]

The FREQoffset value can be calculated by the following equation:

FREQoffset⁢  =  round⁢(foffset⁢× 2ηfXTO) (5)

foffset – RF offset between sub-channels in Hz (0-1,000,000 Hz)

η:
  • 17 for High-band (836-956 MHz)
  • 18 for Low-band (310-477 MHz)

fXTO – XTO frequency in Hz

IF

The IF variable contains the intermediate frequency setting.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00DB

IF[0]

IF[7:0]

0x00DC

IF[1]

IF[15:8]

The IF value can be calculated by the following equation:

IF⁢ =  round(FRFFXTO×2ηFLO_IF) (7)

fRF – RF in Hz

fXTO – XTO frequency in Hz

η:
  • 17 for High-band (836-956 MHz)
  • 18 for Low-band (310-477 MHz)
FLO_IF:
  • 1225 for Low-band 310-318 MHz
  • 1728 for Low-band 418-477 MHz
  • 3457 for High-band 836-956 MHz

RDOCR

The RDOCR variable contains the receive output control settings. For more details on the functional description, see RXMode(buffered) from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00DD

RDOCR

—

0

0

ETRPB

ETRPA

TMDS[1:0]

—

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: Reserved Bit

This bit must always be set to ‘0’.

Bit 5: Reserved Bit

This bit must always be set to ‘0’.

Bit 4: ETRPB – Enable Raw Transparent Output Path B to Pin 19/TRPB

Bit 3: ETRPA – Enable Raw Transparent Output Path A to Pin 16/TRPA

Bits 2..1: TMDS[1:0] – Transparent Mode Data Select

In transparent receive mode, the TMDS bits are irrelevant because the data selection is done by the firmware and the SSM. In buffered receive mode, an additional reshaped transparent output on the 17/TMDO and 19/TMDO_CLOCK pins is activated if at least one of the TMDS bits is set to ‘1’. The active path is automatically selected by the SSM.

Bit 0: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

rssiSysConf

Use the rssiSysConf variable for RSSI enabling/disabling and event signaling. For more details on the functional description, see RSSI Measurement from Related Links

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00DE

rssiSysConf

RssiEnable

—

rssiBufEvMask

RSSIbuf[4:0]

Bit 7: RssiEnable – RSSI Enable

0 = RSSI disabled

1 = RSSI enabled

Bit 6: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 5: rssiBufEvMask – SFIFO Fill Level Event Mask in Receive Mode

0 = No external event on pin 28 (EVENT) is generated if the SFIFO fill level is reached.

1 = An external event on pin 28 (EVENT) is generated if the SFIFO fill level is reached.

Bits 4..0: RSSIbuf[4:0] – SFIFO [4:0] Fill Level Threshold in Receive Mode

rxSetPathA[0], rxSetPathB[0]

The rxSetPathA/B[0] variables are used for RX event signaling and configuration for path A/B. For more details on the functional description, see RXMode(buffered) from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00DF

rxSetPathA[0]

—

rxBufEvMaskA

RXbufA[5:0]

0x00E1

rxSetPathB[0]

—

rxBufEvMaskB

RXbufB[5:0]

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: rxBufEvMaskA/B – DFIFO Fill Level Path A/B in Receive Mode

0 = No external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in receive mode.

1 = An external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in receive mode.

Bits 5..0: RXbufA/B[5:0] – DFIFO A/B [5:0] Fill Level Threshold in Receive Mode

rxSetPathA[1], rxSetPathB[1]

The rxSetPathA/B[1] variables are mainly used for RX telegram handling control for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E0

rxSetPathA[1]

IWUPA

DARA

GAPMA

RXTEHA

———

RXMODA

0x00E2

rxSetPathB[1]

IWUPB

DARB

GAPMB

RXTEHB

———

RXMODB

Bit 7: IWUPA/B – Intermittent WUP Path A/B

0 = Intermittent WUP disabled

1 = Intermittent WUP enabled

Bit 6: DARA/B – Demodulator Automatic Restart on Path A/B

0 = Demodulator automatic restart disabled

1 = Demodulator automatic restart enabled

Bit 5: GAPMA/B – Gap Mode Path A/B

0 = Gap mode disabled

1 = Gap mode enabled

Bit 4: RXTEHA/B – RX Telegram End Handling Path A/B

0 = Return to IDLEMode after EOT

1 = Stay in RXMode after EOT

Bits 3..1: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 0: RXMODA/B – RX Modulation Path A/B

0 = FSK modulation

1 = ASK modulation

rxSysEvent

The rxSysEvent variable contains the configuration masks for the system events. For a functional description, see Event Handling from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E3

rxSysEvent

IDCHKA_Mask

WCOKA_Mask

SOTA_Mask

EOTA_Mask

IDCHKB_Mask

WCOKB_Mask

SOTB_Mask

EOTB_Mask

Bit 7: IDCHKA_Mask – ID Check OK on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if ID check OK on path A.

1 = An external event on pin 28 (EVENT) is generated if ID check OK on path A.

Bit 6: WCOKA_Mask – Wake Check OK on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if wake check OK on path A.

1 = An external event on pin 28 (EVENT) is generated if wake check OK on path A.

Bit 5: SOTA_Mask – Start of Telegram on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if SOT on path A.

1 = An external event on pin 28 (EVENT) is generated if SOT on path A.

Bit 4: EOTA_Mask – End of Telegram on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if EOT on path A.

1 = An external event on pin 28 (EVENT) is generated if EOT on path A.

Bit 3: IDCHKB_Mask – ID Check OK on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if ID check OK on path B.

1 = An external event on pin 28 (EVENT) is generated if ID check OK on path B.

Bit 2: WCOKB_Mask – Wake Check OK on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if wake check OK on path B.

1 = An external event on pin 28 (EVENT) is generated if wake check OK on path B.

Bit 1: SOTB_Mask – Start of Telegram on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if SOT on path B.

1 = An external event on pin 28 (EVENT) is generated if SOT on path B.

Bit 0: EOTB_Mask – End of Telegram on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if EOT on path A.

1 = An external event on pin 28 (EVENT) is generated if EOT on path A.

rxSysSet

The rxSysSet variable is used for enabling and disabling various RXMode features. For more details on the functional description, see General RX Settings from Related Links.

Address Service0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00E4 rxSysSet subChanneling_ENA IdScan_ENA IFAmplifier_ENA PathValidAfterSOT_ENA AntennaDampingPathB _DIS AntennaDampingPathA _DIS switching _SDTX switching _SDRX

Bit 7: subChanneling_ENA – Subchanneling Enable

0 = Disable subchanneling

1 = Enable subchanneling

Bit 6: IdScan_ENA – ID Check Enable

0 = Disable ID check

1 = Enable ID check

Bit 5: IFAmplifier_ENA – IF Amplifier Enable

This bit must always be set to ‘1’ during normal operation.

Bit 4: PathValidAfterSOT_ENA – Path Valid after Start of Telegram Enable

0 = Path valid after SOT disable

1 = Path valid after SOT enable

Bit 3: AntennaDampingPathA_DIS – Antenna Damping on Path A Disable

0 = Enable antenna damping on path A

1 = Disable antenna damping on path A

Bit 2: AntennaDampingPathB_DIS – Antenna Damping on Path B Disable

0 = Enable antenna damping on path B

1 = Disable antenna damping on path B

Bit 1: switching_SDTX – Antenna Switching to Pin 6

0 = Disable pin 6 as SPDT switch input

1 = Enable pin 6 as SPDT switch input

Bit 0: switching_SDRX – Antenna Switching to Pin 3

0 = Disable pin 3 as SPDT switch input

1 = Enable pin 3 as SPDT switch input

SFIDA, SFIDB

The SFIDA/B[3:0] variables are a copy of the start frame ID A/B registers (SFID[4:1]A/B) and contain the start frame ID pattern for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E5

SFIDA[0]

SFID1A[7:0]

0x00E6

SFIDA[1]

SFID2A[7:0]

0x00E7

SFIDA[2]

SFID3A[7:0]

0x00E8

SFIDA[3]

SFID4A[7:0]

0x00E9

SFIDB[0]

SFID1B[7:0]

0x00EA

SFIDB[1]

SFID2B[7:0]

0x00EB

SFIDB[2]

SFID3B[7:0]

0x00EC

SFIDB[3]

SFID4B[7:0]

SFIDCA, SFIDCB

The SFICA/B variables are a copy of the start frame ID configuration registers (SFIDCA/B) and contain the start frame ID configuration for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00ED

SFIDCA

SEMEA

——

SFIDTA[4:0]

0x00EE

SFIDCB

SEMEB

——

SFIDTB[4:0]

Bit 7: SEMEA/B – Serial Mode Enable for Path A/B

0 = Serial Mode Disabled

1 = Serial Mode Enabled

Bits 6..5: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 4..0: SFIDTA/B[4:0] – SFID Threshold for Path A/B

SFIDLA, SFIDLB

The SFIDLA/B variables are a copy of the start frame ID length registers (SFIDLA/B) and contain the start frame ID length settings for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00EF

SFIDLA

——

SFIDLA[5:0]

0x00F0

SFIDLB

——

SFIDLB[5:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 5..0: SFIDLA/B[5:0] – SFID Length for Path A/B (0..32)

SOT1A, SOT1B

The SOT1A/B variables are a copy of the start of telegram conditions 1 registers (SOTC1A/B) and contain the SOT configuration during WUP check for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links. For more details on the hardware description, see RX DSP Control from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F1

SOT1A

WCOBOE

RROEA

SFIDEA

WUPEA

MANOEA

SYTOEA

AMPOEA

CAROEA

0x00F2

SOT1B

WCOAOE

RROEB

SFIDEB

WUPEB

MANOEB

SYTOEB

AMPOEB

CAROEB

Bit 7: WCOB/AOE – Wake Check OK from Path B/A OK Enable

Bit 6: RROEA/B – RSSI Range OK Enable for Path A/B

Bit 5: SFIDEA/B – SFID Match Enable for Path A/B

Bit 4: WUPEA/B – Wake Up Pattern Match Enable for Path A/B

Bit 3: MANOEA/B – Manchester Coding OK Enable for Path A/B

Bit 2: SYTOEA/B – Symbol Timing Check OK Enable for Path A/B

Bit 1: AMPOEA/B – Demodulation Amplitude Check OK Enable for Path A/B

Bit 0: CAROEA/B – Carrier Check OK Enable for Path A/B

SOT2A, SOT2B

The SOT2A/B variables are a copy of the start of telegram conditions 2 registers (SOTC2A/B) and contain the SOT configuration during SOT check for path A and path B. For more details on the functional description, see RX Telegram Handling from Related Links. For more details on the hardware description, see RX DSP Control from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F3

SOT2A

WCOBOE

RROEA

SFIDEA

WUPEA

MANOEA

SYTOEA

AMPOEA

CAROEA

0x00F4

SOT2B

WCOAOE

RROEB

SFIDEB

WUPEB

MANOEB

SYTOEB

AMPOEB

CAROEB

See SOT1A, SOT1B variables for the bit descriptions.

SOTtimeOutA, SOTtimeOutB

The SOTtimeOutA/B variables are a copy of the SOT OK time-out for path A/B registers (SOTTOA/B) and contain the start of telegram time-out configuration for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Sequencer State Machine from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F5

SOTtimeOutA

SOTTOA[7:0]

0x00F6

SOTtimeOutB

SOTTOB[7:0]

Bits 7..0: SOTTOA/B[7:0] – SOT Time-out for Path A/B

SOTTOA/B allows setting time-out periods between approximately 5 µs and 300 ms. A precise formula is given at the corresponding hardware register description.

SYCA, SYCB

The SYCA/B variables are a copy of the symbol check configuration registers (SYCA/B) and contain the symbol check configuration for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Demodulator and Signal Checks from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F7

SYCA

SYTLA[3:0]

SYCSA[3:0]

0x00F8

SYCB

SYTLB[3:0]

SYCSB[3:0]

Bits 7..4: SYTLA/B[3:0] – Symbol Timing Limit for Path A/B

Bits 3..0: SYCSA/B[3:0] – Symbol Check Size for Path A/B

TMUL

The TMUL variable contains the multiplier to calculate temperature compensation of the crystal. For more details on the functional description, see RF Calibration from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00FB

TMUL

TMUL[7:0]

The TMUL value can be calculated by the following equation:

TMUL⁢  =  round⁢ (32⁢ × fRF⁢ / (106⁢⁢ × fSTEP)) (8)

fRF: RF channel frequency

fStep = fXTO / (N x 216)

fXTO – Crystal oscillator frequency

N = 4 for Low-Band (315 MHz/433 MHz)

N = 2 for High-Band (868 MHz/915 MHz)

trxSysConf

The trxSysConf variable contains the enable bits for antenna switching and channel switching. For more details on the functional description, see General RX Settings from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00FC

trxSysConf

————

TRPB_ENA

TRPA_ENA

AntennaSwitching_ENA

ChannelSwitch_ENA

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 3: TRPB_ENA – Transparent RX Path B Enable

This setting is not used by the ATA8210/15 firmware. Use eepServices.RDOCR.ETRPB to activate the raw transparent output on path B.

Bit 2: TRPA_ENA – Transparent RX Path A Enable

This setting is not used by the ATA8210/15 firmware. Use eepServices.RDOCR.ETRPA to activate the raw transparent output on path A.

Bit 1: AntennaSwitching_ENA – Antenna Switching Enable

0 = Disable antenna switching

1 = Enable antenna switching

Bit 0: ChannelSwitch_ENA – Channel Switch Control Enable

0 = Disable channel switch control

1 = Enable channel switch control

WCOtimeOutA, WCOtimeOutB

The WCOtimeOutA/B variables are a copy of the WCO time-out for path A/B registers (WCOTOA/B) and contain the Wake Check OK time-out configuration for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Sequencer State Machine from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0109

WCOtimeOutA

WCOTOA[7:0]

0x010A

WCOtimeOutB

WCOTOB[7:0]

Bits 7..0: WCOTOA/B[7:0] – WCO Time-out for Path A/B

WCOTOA/B allows time-out periods to be set between approximately 5 µs and 300 ms. A precise formula is given at the corresponding hardware register description.

WUPA, WUPB

The WUPA/B[3:0] variables are a copy of the Wake-up Pattern A/B registers (WUP[4:1]A/B) and contain the Wake-up Pattern for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x010B

WUPA[0]

WUP1A[7:0]

0x010C

WUPA[1]

WUP2A[7:0]

0x010D

WUPA[2]

WUP3A[7:0]

0x010E

WUPA[3]

WUP4A[7:0]

0x010F

WUPB[0]

WUP1B[7:0]

0x0110

WUPB[1]

WUP2B[7:0]

0x0111

WUPB[2]

WUP3B[7:0]

0x0112

WUPB[3]

WUP4B[7:0]

WUPLA, WUPLB

The WUPLA/B variables are a copy of the Wake-up Pattern length registers (WUPLA/B) and contain the Wake-up Pattern length settings for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0113

WUPLA

——

WUPLA[5:0]

0x0114

WUPLB

——

WUPLB[5:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 5..0: WUPLA/B[5:0] – WUP Length for Path A/B (0..32)

WUPTA, WUPTB

The WUPTA/B variables are a copy of the Wake-up Pattern threshold registers (WUPTA/B) and contain the Wake-up Pattern threshold for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see Frame Synchronizer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0115

WUPTA

———

WUPTA[4:0]

0x0116

WUPTB

———

WUPTB[4:0]

Bits 7..5: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 4..0: WUPTA/B[4:0] – WUP Threshold for Path A/B

RXCPA[1:0], RXCPB[1:0]

The RXCPA/B[1:0] variables are a copy of the RX CRC polynomial registers (RXCPHA/B and RXCPLA/B) and contain the RX CRC polynomial for path A and path B. For more details on the functional description, see Receive CRC Checker from Related Links. For more details on the hardware description, see RX Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0117

RXCPA[0]

RXCPLA[7:0]

0x0118

RXCPA[1]

RXCPHA[7:0]

0x011E

RXCPB[0]

RXCPLB[7:0]

0x011F

RXCPB[1]

RXCPHB[7:0]

Bits 7..0: RXCPLA/B[7:0] – RX CRC Polynomial Low Byte for Path A/B

Bits 7..0: RXCPHA/B[7:0] – RX CRC Polynomial High Byte for Path A/B

RXCIA[1:0], RXCIB[1:0]

The RXCIA/B[1:0] variables are a copy of the RX CRC initialization registers (RXCIHA/B and RXCILA/B) and contain the RX CRC initialization value for path A and path B. For more details on the functional description, see Receive CRC Checker from Related Links. For more details on the hardware description, see RX Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0119

RXCIA[0]

RXCILA[7:0]

0x011A

RXCIA[1]

RXCIHA[7:0]

0x0120

RXCIB[0]

RXCILB[7:0]

0x0121

RXCIB[1]

RXCIHB[7:0]

Bits 7..0: RXCILA/B[7:0] – RX CRC Init Value Low Byte for Path A/B

Bits 7..0: RXCIHA/B[7:0] – RX CRC Init Value High Byte for Path A/B

RXCSBA, RXCSBB

The RXCSBA/B variables are a copy of the RX CRC skip bits registers (RXCSBA/B) and contain the RX CRC skip bits value for path A and path B. For more details on the functional description, see Receive CRC Checker from Related Links. For more details on the hardware description, see RX Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x011B

RXCSBA

RXCSBA[7:0]

0x0122

RXCSBB

RXCSBB[7:0]

Bits 7..0: RXCSBA/B[7:0] – RX CRC Skip Bit Number for Path A/B

RXTLA[1:0], RXTLB[1:0]

The RXTLA/B[1:0] variables are a copy of the RX telegram length registers (RXTLHA/B and RXTLLA/B) and contain the telegram length setting in RXMode(buffered) for path A and path B. For more details on the functional description, see Telegram Settings and Signal Checks from Related Links. For more details on the hardware description, see RX Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x011C

RXTLA[0]

RXTLLA[7:0]

0x011D

RXTLA[1]

————

RXTLHA[3:0]

0x0123

RXTLB[0]

RXTLLB[7:0]

0x0124

RXTLB[1]

————

RXTLHB[3:0]

Bits 7..0: RXTLLA/B[7:0] – RX Telegram Length Low Byte for Path A/B

Bits 3..0: RXTLHA/B[3:0] – RX Telegram Length High Byte for Path A/B

RXBC1

The RXBC1 variable is a copy of the RX buffer control 1 register (RXBC1) and contains the settings for the RX buffer configuration for path A and path B. For more details on the functional description, see General RX Settings from Related Links. For more details on the hardware description, see RX Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0125

RXBC1

RXMSBB

RXCBLB[1:0]

RXCEB

RXMSBA

RXCBLA[1:0]

RXCEA

Bit 7: RXMSBB – RX MSB First for Path B

Bits 6..5: RXCBLB[1:0] – RX CRC Bit Length for Path B

Bit 4: RXCEB – RX CRC Enable for Path B

Bit 3: RXMSBA – RX MSB First for Path A

Bits 2..1: RXCBLA[1:0] – RX CRC Bit Length for Path A

Bit 0: RXCEA – RX CRC Enable for Path A

RSSC

The RSSC variable is a copy of the receive signal strength configuration register (RSSC) and contains the control settings of the RSSI buffer. For more details on the functional description, see RSSI Measurement from Related Links. For more details on the hardware description, see RSSI Buffer from Related Links.

Address Service0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0138

RSSC

—

RSPKF

RSHRX

RSWLH

RSUP[3:0]

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: RSPKF – RSSI Peak Values to SFIFO

Bit 5: RSHRX – RSSI High Band Reception

Bit 4: RSWLH – RSSI Within Low and High Limits

Bits 3..0: RSUP[3:0] – RSSI Update Period