4.4.3.2.1.11 SYCA – Symbol Check
Configuration for Path A
| Name: | SYCA |
| Offset: | 0x09E |
| Reset: | 0x00 |
The symbol check
duration and timing are configured by the settings in this register for path A. This
register must only be modified if the block receiving the settings is disabled
(RDPR.PRPTA = 1). Modifying the settings during operation may lead to
unstable operation.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | SYTLA[3:0] | SYCSA[3:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:4 – SYTLA[3:0] Symbol Timing Limit
for Path A
SYTLA sets the
timing limits for the allowed tolerance of the actual symbol edge transition versus
the expected position. The expected symbol edge position is derived from the clock
recovery circuit. The following table shows the allowed tolerance as a percentage of
the symbol duration. Values below 25% are not recommended because the edge to edge
jitter can be in this range and therefore might lead to false error indication.
Table 4-26. Allowed Symbol Edge Tolerance versus SYTLA| Allowed Symbol Edge Tolerance ± | SYTLA |
|---|
| 0% | 0 |
| 3% | 1 |
| 6% | 2 |
| 9% | 3 |
| 13% | 4 |
| 16% | 5 |
| 19% | 6 |
| 22% | 7 |
| Tight – 25% | 8 |
| 28% | 9 |
| 31% | 10 |
| Default – 34% | 11 |
| 38% | 12 |
| 41% | 13 |
| 44% | 14 |
| Lax – 47% | 15 |
Bits 3:0 – SYCSA[3:0] Symbol Check Size for Data Path A
The SYCSA bits configure the
number of symbols checked for the symbol check OK signals (SOTSA.MANOA, SOTSA.SYTOA,
SOTSA.AMPOA, SOTSA.CAROA). A SYCSA value of 6 is a good setting for avoiding
unwanted wake-ups. Lower values lead to laxer checking; higher values subject the
incoming signal to a more severe check.
Table 4-27. Number of Symbols
Checked versus SYCSA| Number of Symbols Checked | SYCSA |
|---|
| Check Disabled | 0 |
| 1 | 1 |
| 3 | 2 |
| 5 | 3 |
| 7 | 4 |
| 9 | 5 |
| 11 | 6 |
| 13 | 7 |
| 15 | 8 |
| 17 | 9 |
| 19 | 10 |
| 21 | 11 |
| 23 | 12 |
| 25 | 13 |
| 27 | 14 |
| 29 | 15 |
