17.14.10 General Timer/Counter Control Register

Name: GTCCR
Offset: 0x2F
Reset: 0x00
Property: -

Bit 76543210 
 TSM     REMAPPSR 
Access R/WR/WR/W 
Reset 000 

Bit 7 – TSM Timer/Counter Synchronization Mode

Writing the TSM bit to '1' activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to '0', the PSR bit is cleared by hardware, and the Timer/Counter start counting.

Bit 1 – REMAP

This bit controls how the TIMER pins are mapped to pins as shown in the table:
REMAPTO_CLKOC0BOC0AICP0NOTE
0PA0PA1PB1PB2DEFAULT
1PB3PA5PA3PA4REMAPPED

Bit 0 – PSR Prescaler 0 Reset Timer/Counter 0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.