17.14.1 Timer/Counter0 Control Register A
| Name: | TCCR0A |
| Offset: | 0x2E |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COM0An[1:0] | COM0Bn[1:0] | WGM0n[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 7:6 – COM0An[1:0] Compare Output Mode for Channel A [n = 1:0]
Bits 5:4 – COM0Bn[1:0] Compare Output Mode for Channel B [n = 1:0]
The COM0A[1:0] and COM0B[1:0] control the Output Compare pins (OC0A and OC0B respectively) behavior. If one or both of the COM0A[1:0] bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM0B[1:0] bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver.
When the OC0A or OC0B is connected to the pin, the function of the COM0x[1:0] bits is dependent of the WGM0[3:0] bits setting. The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to a Normal or a CTC mode (non-PWM).
| COM0A1/COM0B1 | COM0A0/COM0B0 | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A/OC0B disconnected. |
| 0 | 1 | Toggle OC0A/OC0B on Compare Match. |
| 1 | 0 | Clear OC0A/OC0B on Compare Match (Set output to low level). |
| 1 | 1 | Set OC0A/OC0B on Compare Match (Set output to high level). |
The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the fast PWM mode.
| COM0A1/COM0B1 | COM0A0/COM0B0 | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A/OC0B disconnected. |
| 0 | 1 |
WGM0[3:0]=0: Normal port operation, OC0A/OC0B disconnected WGM0[3:0]=1: Toggle OC0A on compare match, OC0B reserved |
| 1(1) | 0 | Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM (non-inverting mode) |
| 1(1) | 1 | Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM (inverting mode) |
- A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode.
| COM0A1/COM0B1 | COM0A0/COM0B0 | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A/OC0B disconnected. |
| 0 | 1 |
WGM0[3:0]=0: Normal port operation, OC0A/OC0B disconnected WGM0[3:0]=1: Toggle OC0A on compare match, OC0B reserved |
| 1(1) | 0 | Clear OC0A/OC0B on Compare Match when up-counting. Set OC0A/OC0B on Compare Match when down-counting. |
| 1(1) | 1 | Set OC0A/OC0B on Compare Match when up-counting. Clear OC0A/OC0B on Compare Match when down-counting. |
- A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. Refer to Phase Correct PWM Mode for details.
Bits 1:0 – WGM0n[1:0] Waveform Generation Mode [n = 1:0]
Combined with the WGM0[3:2] bits found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation).
| Mode | WGM0[3:0] | Timer/Counter Mode of Operation | TOP | Update of OCR0x at | TOV0 Flag Set on | |||
|---|---|---|---|---|---|---|---|---|
| 0 | 0000 | Normal | 0xFFFF | Immediate | MAX | |||
| 1 | 0001 | PWM, Phase Correct, 8-bit | 0x00FF | TOP | BOTTOM | |||
| 2 | 0010 | PWM, Phase Correct, 9-bit | 0x01FF | TOP | BOTTOM | |||
| 3 | 0011 | PWM, Phase Correct, 10-bit | 0x03FF | TOP | BOTTOM | |||
| 4 | 0100 | CTC (Clear Timer on Compare) | OCR0A | Immediate | MAX | |||
| 5 | 0101 | Fast PWM, 8-bit | 0x00FF | TOP | TOP | |||
| 6 | 0110 | Fast PWM, 9-bit | 0x01FF | TOP | TOP | |||
| 7 | 0111 | Fast PWM, 10-bit | 0x03FF | TOP | TOP | |||
| 8 | 1000 | PWM, Phase and Frequency Correct | ICR0 | BOTTOM | BOTTOM | |||
| 9 | 1001 | PWM, Phase and Frequency Correct | OCR0A | BOTTOM | BOTTOM | |||
| 10 | 1010 | PWM, Phase Correct | ICR0 | TOP | BOTTOM | |||
| 11 | 1011 | PWM, Phase Correct | OCR0A | TOP | BOTTOM | |||
| 12 | 1100 | CTC (Clear Timer on Compare) | ICR0 | Immediate | MAX | |||
| 13 | 1101 | Reserved | - | - | - | |||
| 14 | 1110 | Fast PWM | ICR0 | TOP | TOP | |||
| 15 | 1111 | Fast PWM | OCR0A | TOP | TOP | |||