31.20.17 PMC Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: PMC_IMR
Offset: 0x006C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   XT32KERR  CFDEVMOSCRCSMOSCSELS 
Access RRRR 
Reset 0000 
Bit 15141312111098 
 PCKRDY7PCKRDY6PCKRDY5PCKRDY4PCKRDY3PCKRDY2PCKRDY1PCKRDY0 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
  LOCKU  MCKRDY LOCKAMOSCXTS 
Access RRRR 
Reset 0000 

Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask

Bit 18 – CFDEV Clock Failure Detector Event Interrupt Mask

Bit 17 – MOSCRCS Main RC Status Interrupt Mask

Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask

Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt Mask

Bit 6 – LOCKU UTMI PLL Lock Interrupt Mask

Bit 3 – MCKRDY Host Clock Ready Interrupt Mask

Bit 1 – LOCKA PLLA Lock Interrupt Mask

Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Mask