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31.20.17 PMC Interrupt Mask Register
The following configuration values are valid for all listed bit
names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name: PMC_IMR Offset: 0x006C Reset: 0x00000000 Property: Read-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 XT32KERR CFDEV MOSCRCS MOSCSELS Access R R R R Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 LOCKU MCKRDY LOCKA MOSCXTS Access R R R R Reset 0 0 0 0
Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt
Mask
Bit 18 – CFDEV Clock Failure Detector Event Interrupt
Mask
Bit 17 – MOSCRCS Main RC Status Interrupt
Mask
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status
Interrupt Mask
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt
Mask
Bit 6 – LOCKU UTMI PLL Lock Interrupt
Mask
Bit 3 – MCKRDY Host Clock Ready Interrupt
Mask
Bit 1 – LOCKA PLLA Lock Interrupt
Mask
Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt
Mask
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