31.20.9 PMC Clock Generator Main Clock Frequency Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | CKGR_MCFR |
| Offset: | 0x0024 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CCSS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RCMEAS | MAINFRDY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MAINF[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MAINF[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 24 – CCSS Counter Clock Source Selection
| Value | Description |
|---|---|
| 0 | The measured clock of the MAINF counter is the Main RC oscillator. |
| 1 | The measured clock of the MAINF counter is the Main crystal oscillator. |
Bit 20 – RCMEAS RC Oscillator Frequency Measure (write-only)
The measurement is performed on the main frequency (i.e., not limited to the Main RC oscillator only). If the source of MAINCK is the Main crystal oscillator, the restart of measurement may not be required because of the stability of crystal oscillators.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Restarts measuring of the frequency of MAINCK. MAINF carries the new frequency as soon as a low-to-high transition occurs on the MAINFRDY flag. |
Bit 16 – MAINFRDY Main Clock Frequency Measure Ready
| Value | Description |
|---|---|
| 0 | MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by means of RCMEAS. |
| 1 | The measured oscillator has been enabled previously and MAINF value is available. Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at ‘1’ then another read access must be performed on the register to get a stable value on the MAINF field. |
Bits 15:0 – MAINF[15:0] Main Clock Frequency
Gives the number of cycles of the clock selected by the bit CCSS within 16 SLCK periods. To calculate the frequency of the measured clock:
fSELCLK = (MAINF x fSLCK)/16
where frequency is in MHz.