31.20.29 PMC SleepWalking Enable Register 1

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

Name: PMC_SLPWK_ER1
Offset: 0x0134
Property: Write-only

Bit 3130292827262524 
 PID63PID62 PID60PID59PID58PID57PID56 
Access WWWWWWW 
Reset 0000000 
Bit 2322212019181716 
   PID53PID52PID51PID50PID49PID48 
Access WWWWWW 
Reset 000000 
Bit 15141312111098 
 PID47PID46PID45PID44PID43PID42PID41PID40 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 PID39 PID37      
Access WW 
Reset 00 

Bits 30, 31 – PIDx Peripheral SleepWalking x Enable

ValueDescription
0 No effect.
1

The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”

Bits 24, 25, 26, 27, 28 – PIDx Peripheral SleepWalking x Enable

ValueDescription
0 No effect.
1

The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”

Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PIDx Peripheral SleepWalking x Enable

ValueDescription
0 No effect.
1

The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”

Bit 5 – PIDx Peripheral SleepWalking x Enable

ValueDescription
0 No effect.
1

The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”