31.20.13 PMC Programmable Clock Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Name: | PMC_PCKx [x=0..7] |
Offset: | 0x0040 |
Reset: | 0 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PRES[7:4] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PRES[3:0] | CSS[2:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 11:4 – PRES[7:0] Programmable Clock Prescaler
Value | Description |
---|---|
0–255 | Selected clock is divided by PRES+1. |
Bits 2:0 – CSS[2:0] Programmable Clock Source Selection
Value | Name | Description |
---|---|---|
0 | SLOW_CLK | SLCK is selected |
1 | MAIN_CLK | MAINCK is selected |
2 | PLLA_CLK | PLLACK is selected |
3 | UPLL_CLK | UPLLCKDIV is selected |
4 | MCK | MCK is selected |
5 | AUDIO_CLK | AUDIOPLLCLK is selected |