1.6.6 Simulation Flow

The following steps describe the simulation flow:

  1. Initially, the transceiver is at reset.
  2. The Pattern_gen block sends 40-bit wide K28.5 pattern to the transceiver.
  3. Transmitter lanes are connected to receiver lanes internally in the testbench stimulus.
  4. The Bit_slip_shift module receives data from transceiver and asserts RX_SLIP port until symbol alignment occurs and then asserts valid_signal.
  5. After symbol alignment, pattern_gen block starts sending incremental counter pattern and pattern_chk block starts checking the receiver data.

The following figures show the simulation waveform for the PMA design highlighting pattern_chk block status signals and Tx/Rx PRBS data lock. The simulation run time will be 72 us approximately.

Figure 1-14. Simulation Waveform for PMA Design Highlighting CDR Bit-slip Status
Figure 1-15. Simulation Waveform for PMA Design Highlighting Pattern Checker Lock