1.6.5 Simulating the Design

The pattern generator module generates an incremental counter pattern used to drive the transceiver in PMA mode. If data mismatch occurs, the pattern checker checks the received counter data and generates error flags.

For simulation, perform the following the steps:

1. Open Libero SoC design built through the TCL scripts.
2. To run the simulation, navigate to Stimulus Hierarchy, right-click the top.v file, and select Set as active stimulus.
3. In the Design Flow tab, double-click Simulate under Verify Pre-Synthesized Design to simulate the design, as shown in the following figure.