1.6.4 Port Description
(Ask a Question)The following table lists the important ports for the PMA design.
| Port | Direction | Description |
|---|---|---|
| LANE0_RXD_P | Input | Transceiver Receiver differential input |
| LANE0_RXD_N | Input | Transceiver Receiver differential input |
| LANE0_PCS_ARST_N | Input | Asynchronous active-low reset for the PCS lane |
| LANE0_PMA_ARST_N | Input | Asynchronous active-low reset for the PMA lane |
| LANE0_RX_SLIP | Input | Rising-edge requests for the transceiver lane to CDR slip the parallel boundary by one bit |
| LANE0_TXD_P | Output | Transceiver Transmitter differential output |
| LANE0_TXD_N | Output | Transceiver Transmitter differential output |
| LANE0_RX_CLK_R | Output | Regional receive clock to fabric |
| LANE0_TX_CLK_R | Output | Regional transmit clock to fabric |
| LANE0_TX_CLK_STABLE | Output | Transmits transceiver/PCS lane ready flag |
| LANE0_RX_READY | Output | Receives transceiver/PCS lane ready flag |
| LANE0_RX_VAL | Output | Receives data valid flag associated with a lane |
| LANE0_RX_IDLE | Output | Receives electrical-idle detection flag |