1.4.5 Simulation Flow

The following steps describe the simulation flow:

  1. Initially, the transceiver is at reset.
  2. The pattern_gen_0 block sends incremental counter pattern with K28.5 character to the transceiver.
  3. Transmitter lanes are connected to receiver lanes internally in the testbench stimulus.
  4. The pattern_chk_0 block waits for valid data and checks the receiver data.
  5. The Generate_err_i input can be pulsed to send 32'hFFFFFFEF instead of the counter pattern. 
This increments the error_count_o[31:0].

The following figures show the simulation waveform for the 8b10b design highlighting pattern checker status signals and Tx/Rx data match. The simulation run time will be 58 us approximately.

Figure 1-4. Simulation Waveform for 8b10b Design Highlighting Pattern Checker Status
Figure 1-5. Simulation Waveform for 8b10b Design Highlighting Tx and Rx Data Match