1.4.3 Port Description

The following table lists the important ports for the design.

Table 1-2. 8b10b Port List
Port	Direction	Description
LANE0_RXD_P	Input	Transceiver receiver differential input
LANE0_RXD_N	Input	Transceiver receiver differential input
REF_CLK_PAD_P	Input	Transmit PLL input clock from reference clock interface
REF_CLK_PAD_N	Input	Transmit PLL input clock from reference clock interface
LANE0_PCS_ARST_N	Input	Asynchronous active-low reset for the PCS lane
generate_err_i	Input	Injecting error, active high
clear_i	Input	Error counter clear input, active high
LANE0_TXD_P	Output	Transceiver transmitter differential output
LANE0_TXD_N	Output	Transceiver transmitter differential output
LANE0_RX_CLK_R	Output	Regional receive clock to fabric
LANE0_TX_CLK_R	Output	Regional transmit clock to fabric
LANE0_RX_VAL	Output	Receiver data valid flag associated with a lane
error_o	Output	Error flags
lock_o	Output	Data lock flag
error_count_o[31:0]	Output	Error count flags

AN4662