22. Module: CPU

An address error trap is generated in Indirect Register Offset Addressing mode (represented as [Ws + Wb] within instructions) when the value of Ws (Source) used is beyond 24 bits wide (size of the address path). The issue may occur even when the effective address (Ws + Wb) is a valid address.

Work around

Either of the following workarounds can be used to overcome the issue:

  1. Define the value of Ws within the 24-bit address range.
  2. When using the XC-DSC V3.20 or newer C Compiler for dsPIC® DSCs, enable the compiler option: -merrata=base_offset (Project Properties>XC_DSC>xc-dsc-gcc>Additonal options).
Affected Silicon Revisions
A1
A2
X