Introduction

The dsPIC33AK512MPS512 family devices that you have received conform functionally to the current device data sheet (DS70005591D), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table . The silicon issues are summarized in Table .

The errata described in this document will be addressed in future revisions of the dsPIC33AK512MPS512 family silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table apply to the current silicon revision (A2).

Data sheet clarifications and corrections start on Data Sheet Clarifications, following the discussion of silicon issues.

The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate website (www.microchip.com).

To determine the silicon revision level using MPLAB IDE with a hardware debugger, follow these steps:

  1. Connect the device to the hardware debugger using the appropriate interface.
  2. Open an MPLAB® X IDE project.
  3. Configure the MPLAB X IDE project for the correct device and hardware debugger.
  4. In MPLAB X IDE, navigate to Window > Dashboard, and then click the Refresh Debug Tool Status icon ( ).
  5. The part number and Device Revision ID value appear in the Output window, depending on the development tool used.
    Note: If you cannot retrieve the silicon revision level, contact your local Microchip sales office for support.

The following table lists the DEVREV values for the various silicon revisions of the dsPIC33AK512MPS512 family.

Table . Silicon DEVREV Values
Part NumberDevice ID (1)Revision ID for Silicon Revision (1)Part NumberDevice ID (1)Revision ID for Silicon Revision (1)
A1A2A1A2
dsPIC33AK512MPS5120xA77C01h02hdsPIC33AK256MPS2060xA71901h02h
dsPIC33AK512MPS5100xA77BdsPIC33AK256MPS2050xA718
dsPIC33AK512MPS5080xA77AdsPIC33AK512MC5100xA763
dsPIC33AK512MPS5060xA779dsPIC33AK512MC5080xA762
dsPIC33AK512MPS5050xA778dsPIC33AK512MC5060xA761
dsPIC33AK256MPS5120xA75CdsPIC33AK512MC5050xA760
dsPIC33AK256MPS5100xA75BdsPIC33AK256MC5100xA743
dsPIC33AK256MPS5080xA75AdsPIC33AK256MC5080xA742
dsPIC33AK256MPS5060xA759dsPIC33AK256MC5060xA741
dsPIC33AK256MPS5050xA758dsPIC33AK256MC5050xA740
dsPIC33AK512MPS2120xA73CdsPIC33AK512MC2100xA723
dsPIC33AK512MPS2100xA73BdsPIC33AK512MC2080xA722
dsPIC33AK512MPS2080xA73AdsPIC33AK512MC2060xA721
dsPIC33AK512MPS2060xA739dsPIC33AK512MC2050xA720
dsPIC33AK512MPS2050xA738dsPIC33AK256MC2100xA703
dsPIC33AK256MPS2120xA71CdsPIC33AK256MC2080xA702
dsPIC33AK256MPS2100xA71BdsPIC33AK256MC2060xA701
dsPIC33AK256MPS2080xA71AdsPIC33AK256MC2050xA700
Note:
  1. Refer to the “dsPIC33AK512MPS512 Family Flash Programming Specification” for detailed information on Device and Revision IDs for your specific device.
Table . Silicon Issue Summary
ModuleFeatureItem NumberIssue SummaryAffected Revisions (1,2)
A1A2
CPUPCTRAP1PCTRAP captures the trap origination address of a math error trap even when disabled.XX
DMABus Read Error2DMA Bus Read Error Fault bit not set.XX
PWMPCI3PCI active is not terminated in latched edge detection modes.XX
PWMComplementary Mode4Software Override priority is not maintained over current limit PCI (CLPCI).XX
PWMComplementary Mode5

Dead time is not applied properly when the PCI active signal is deasserted for a short time of 1-2 PWM clock cycles.

XX
PWMPCI6PCI SR latch does not reset in RESET Dominant mode.XX
PWMEOC7In Retriggerable mode, EOC event is not blocked when the retrigger event is close to EOC.XX
PWMLEB8LEB active signal asserts for two clocks less than programmed.XX
PWMTime Base Capture9Manual time base capture fails after the first capture event.XX
PWMTRIGx10When TRIGx = EOC and CAHALF is changed by software, a trigger event can occur in the opposite phase.XX
PWMPCI 11In Complementary Output mode, when PSYNC is enabled in PCI Edge Detect mode, the PCI override can be applied twice.XX
ITCCVD Array12Make-before-break issue with CVD/cap array.XX
ITCRX Guard Pins13Guard settings in ITCRECx registers control the wrong pins.XX
QEIIndex Event14Index event is missed when the clock divider (INTDIV[2:0]) is configured for greater than 1.XX
QEI Index Counter15Position counter is loaded with 0x00000001 on an index event for PIMOD[2:0] = 0b001.XX
QEIBuffer Overflow16Address is not causing the buffer overflow in Address Detect mode.XX
CCPOutput17When ASDGM = 1, the CCP generates an output with the shutdown gate input at 0.XX
CCPCapture18When CCSEL= 1 and IGSM= 1, CCP will capture the timer value without an edge.XX
PTGSoftware Trigger19PTGSWT bit is not cleared in hardware.XX
PWMADC Trigger Events20In LLC mode, when TRIGy is equal to EOC and with CAPTREN is set, ADC triggers are not generated when ADC trigger source is TRIGy.XX
DACDACOUT Buffers21Both DAC output buffers are non-linear near the supply rails.X
CPUTrap22Address error trap generated on legal indirect+offset move.X
GPIOIO Current Limit23Source/Sink capability of IO pins is less than electrical specifications.X
SPIIgnore Overflow24SPI receiver does not continue to run on overflow with the Ignore Overflow bit set.XX
SILICONSilicon Temperature Variants25Silicon only supports Industrial temp (-40°C to 85°C) and not Extended temp (-40°C to 125°C).X
CPUInterrupt Vectoring26Interrupt vectoring and simultaneous PBU/cache invalidation may stall the CPU indefinitely.XX
SPIHost Mode27SPI Host mode may exhibit unreliable operation when using the peripheral bus clock.XX
In-Circuit DebuggerBreakpoints28If a hardware breakpoint is placed immediately after a conditional branch instruction, the breakpoint can be missed and will result in no debugger halt.XX
Note:
  1. Only the issues marked with an “X” in the last column apply to the current silicon revision.
  2. If the column cell is unmarked or blank, it indicates the issue is resolved in the latest revised silicon.