6.4.2 NVM Unlock Sequence

The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations:
  • Program Flash Memory Row Erase
  • Load of Program Flash Memory write latches
  • Write of Program Flash Memory write latches to program memory
  • Write of Program Flash Memory write latches to User IDs
  • Write to EEPROM
The unlock sequence consists of the following steps and must be completed in order:
  • Write 0x55 to NVMCON2
  • Write 0xAA to NMVCON2
  • Set the WR bit of NVMCON1
Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction.
Important: The two NOP instructions after setting the WR bit, that were required in previous devices, are not required for PIC16(L)F184XX devices. See Figure 6-2 for an example of the unlock sequence.

Since the unlock sequence must not be interrupted, global interrupts must be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

Figure 6-2. NVM Unlock Sequence Flowchart

NVM Unlock Sequence

   BCF      INTCON, GIE       ; Recommended to prevent interruptions
   BANKSEL  NVMCON1           ;
   BSF      NVMCON1, WREN     ; Enable write/erase
   MOVLW    55h               ; Load 55h
   MOVWF    NVMCON2           ; Step 1: Load 55h into NVMCON2
   MOVLW    AAh               ; Step 2: Load W with AAh
   MOVWF    NVMCON2           ; Step 3: Load AAH into NVMCON2
   BSF      NVMCON1, WR       ; Step 4: Set WR bit to begin write/erase
   BSF      INTCON, GIE       ; Re-enable interrupts
Note:
  1. Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
  2. Opcodes shown are illustrative; any instruction that has the indicated effect may be used.