6.4.7 NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration Words

NVMREGS can be used to access the following memory regions:
  • Device Information Area (DIA)
  • Device Configuration Information (DCI)
  • User ID region
  • Device ID and Revision ID
  • Configuration Words
  • EEPROM

The value of NVMREGS is set to ‘1’ in the NVMCON1 register to access these regions. The memory regions listed above would be pointed to by PC[15] = 1, but not all addresses reference valid data. Different access may exist for reads and writes. Refer to the table below. When read access is initiated on an address outside the parameters listed in the following table, the NVMDATH: NVMDATL register pair is cleared, reading back ‘0’s.

Table 6-2. NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration Words (NVMREGS = 1)
Address Function Read Access Write Access
0x8000 - 0x8003 User IDs Yes Yes
0x8005 - 0x8006 Device ID/Revision ID Yes No
0x8007 - 0x800B Configuration Words 1-5 Yes Yes
0x8100 - 0x82FF DIA and DCI Yes No
0xF000 - 0xF0FF EEPROM Yes Yes

Device ID Access

   ; This write routine assumes the following:
   ; 1. A full row of data are loaded, starting at 
   ; the address in DATA_ADDR
   ; 2. Each word of data to be written is made up of
   ; two adjacent bytes in DATA_ADDR, stored in little endian format
   ; 3. A valid starting address (the Least Significant bits = 00000)
   ; is loaded in ADDRH:ADDRL
   ; 4. ADDRH and ADDRL are located in common RAM (locations 0x70-0x7F)
   ; 5. NVM interrupts are not taken into account

      BANKSEL    NVMADRH
      MOVF       ADDRH,W
      MOVWF      NVMADRH             ; Load initial address
      MOVF       ADDRL,W
      MOVWF      NVMADRL
      MOVLW      LOW DATA_ADDR       ; Load initial data address
      MOVWF      FSR0L
      MOVLW      HIGH DATA_ADDR
      MOVWF      FSR0H
      BCF        NVMCON1,NVMREGS     ; Set PFM as write location
      BSF        NVMCON1,WREN        ; Enable writes
      BSF        NVMCON1,LWLO        ; Load only write latches

   LOOP
      MOVIW      FSR0++
      MOVWF      NVMDATL             ; Load first data byte
      MOVIW      FSR0++
      MOVWF      NVMDATH             ; Load second data byte
      CALL       UNLOCK_SEQ          ; If not, go load latch
      INCF       NVMADRL,F           ; Increment address
      MOVF       NVMADRL,W
      XORLW      0x1F                ; Check if lower bits of address 
                                     ; are 00000
      ANDLW      0x1F                ; and if on last of 32 addresses
      BTFSC      STATUS,Z            ; Last of 32 words?
      GOTO       START_WRITE         ; If so, write latches to memory
      GOTO       LOOP

   START_WRITE
      BCF        NVMCON1,LWLO        ; Latch writes complete, 
                                     ; Now write memory
      CALL       UNLOCK_SEQ          ; Perform required unlock sequence
      BCF        NVMCON1,LWLO        ; Disable writes
	
   UNLOCK_SEQ
      MOVLW      0x55
      BCF        INTCON,GIE          ; Disable interrupts
      MOVWF      NVMCON2             ; Begin unlock sequence
      MOVLW      0xAA
      MOVWF      NVMCON2
      BSF        NVMCON1,WR
      BSF        INTCON,GIE          ; Re-enable interrupts
                                     ; Unlock sequence complete
      RETURN