32.5.2 Precharge Control
The Precharge stage is an optional period of time that brings the
external channel and internal Sample-and-Hold capacitor to known voltage levels. Precharge
is enabled by writing a nonzero value to the ADPRE register. This stage is initiated when
an ADC conversion begins, either from setting the GO bit, a special
event trigger, or a conversion restart from the computation functionality. If the ADPRE
register is cleared when an ADC conversion begins, this stage is skipped.
During the precharge time, CHOLD is disconnected from the outer portion of the sample path that leads to the external capacitive sensor and is connected to either VDD or VSS, depending on the value of the PPOL bit. At the same time, the port pin logic of the selected analog channel is overridden to drive a digital high or low out, in order to precharge the outer portion of the ADC’s sample path, which includes the external sensor. The output polarity of this override is also determined by the PPOL bit. The amount of time that this charging needs is controlled by the ADPRE register.
Important: The external charging overrides the TRIS setting
of the respective I/O pin. If there is a device attached to this pin, Precharge may not be
used.