32.8.16 ADCON1
| Name: | ADCON1 |
| Offset: | 0x112 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PPOL | IPEN | GPOL | DSEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – PPOL Precharge Polarity bit
| Value | Name | Description |
|---|---|---|
x |
PRE = 0 |
Bit has no effect |
1 |
PRE > 0 & ADC input is I/O
pin |
Pin shorted to AVDD |
0 |
PRE > 0 & ADC input is I/O
pin |
Pin shorted to VSS |
1 |
PRE > 0 & ADC input is
internal |
CHOLD Shorted to AVDD |
0 |
PRE > 0 & ADC input is
internal |
CHOLD Shorted to VSS |
Bit 6 – IPEN A/D Inverted Precharge Enable bit
| Value | Name | Description |
|---|---|---|
x |
DSEN =
0 |
Bit has no effect |
1 |
DSEN =
1 |
The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle |
0 |
DSEN =
1 |
Both conversion cycles use the precharge and guards specified by PPOL and GPOL |
Bit 5 – GPOL Guard Ring Polarity Selection bit
| Value | Description |
|---|---|
1 |
ADC guard Ring outputs start as digital high during Precharge stage |
0 |
ADC guard Ring outputs start as digital low during Precharge stage |
Bit 0 – DSEN Double-Sample Enable bit
| Value | Description |
|---|---|
1 |
Two conversions are performed on each trigger. Data from the first conversion appears in PREV. |
0 |
One conversion is performed for each trigger |