20.8.7 Edge-Triggered Hardware Limit One Shot Mode

In Edge-Triggered Hardware Limit One Shot modes, the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows:

• Rising edge start and Reset (MODE[4:0] = 01100)
• Falling edge start and Reset (MODE[4:0] = 01101)

The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 20-9 illustrates the rising edge hardware limit one-shot operation.

When this mode is used in conjunction with the CCP, the first starting edge trigger and all subsequent Reset edges will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value, and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs.

Note:

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.