48.20 Rev. D – 09/2014
| Block Diagram | |
| NVM Controller bus connection changed from Master to Slave. | |
| Clock System | |
| Register Synchronization updated by splitting the section into Common synchronizer Register Synchronization and Distributed Synchronizer Register Synchronization. | |
| Electrical Characterstics | |
| ADC Characteristics | : Added note
defining gain accuracy parameter in: - ADC Differential Mode, Differential Mode (Device Variant) ADC Single-Ended Mode, Single-Ended Mode (Device Variant A) |
| Errata | |
| Updated errata for revision A, B and C: Added Errata Reference 13140, 12860. | |