48.2 Revision G - April 2021

This revision includes the updates as listed in the following table, and numerous typographical corrections throughout the document.


Section	Description
General	The SPI, I²S, and I²C standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively. These terms have been updated throughout this document for this revision.
Features	Updated RWW to RWWEE for Memories
Ordering Information	Updated RWW to RWWEE in the Device Variant description
Pinout	Updated the following Pinouts to accurately display the RESET pin QFN48 QFN32 / TQFP32 UFBGA64 WLCSP45 WLCSP35
I/O Multiplexing	Added a new notes to table 7-1 for SERCOM and TCC3 availability Added a new note to table 7-2 for TCC3 availability Removed erroneous text from the header of Table 7-5 in SERCOM I²C Pins
Product Mapping	Updated RWW to RWWEE in the figure
Memories	Updated EEPROM and RWWEE text in Embedded Memories Updated RWW to RWWEE in all the tables in Physical Memory Map Updated Table 10-7 in NVM User Row Mapping to display text for Emulation
Processor and Architecture	Updated the Addresses of the bits in SRAM Quality of Service Updated the following registers, changing clear to set: PCA0 Register WPSET PCA1 Register WPSET PCA2 Register WPSET
DSU	Added verbiage for RWWEE Emulation to Chip Erase Updated table 13-3 in 32-bit Cyclic Redundancy Check CRC32 with proper capitalization on Emulation Updated table 13-6 in System Services Availability when Accessed Externally and Device is Protected with the correct RWWEE verbiage Updated the DEVSEL bit of the DID Register with information for Device identification
Clock System	Updated Read Request with new verbiage for the READREQ.RCONT and READREQ.RREQ bits
GCLK	Updated the GENDIV Register with a new Register property, and added a new column for the Maximum Division Factor to the table for the DIV bit.
SYSCTRL	Updated the following registers: XOSC with new verbiage for the AMPGC and GAIN bits DFLLCTRL - removed erroneous RUNSTDBY bit
RTC	Updated the Overview with new verbiage for clock sources selectable through the GCLK.
DMAC	Updated the following registers: BASEADDR with new text for the bitfield BASEADDR WRBADDR with new text for the bitfield WRBADDR SRCADDR with new text for the bitfield SRCADDR DSTADDR with new text for the bitfield DSTADDR DESCADDR bitfield was updated for 64 bit alignment in the DESCADDR register
EIC	Updated the EXTINTx bit of the INTENCLR register to read “disables the external interrupt.”
NVMCTRL	Updated the Overview with new text for the EEPROM Emulation array Updated Memory Organization with new EEPROM Emulation verbiage Updated NVM User Configuration with new EEPROM Emulation verbiage Updated the following registers: PARAM The ADDR bit of the ADDR Register was updated with new verbiage The LOCK bit of the LOCK Register was updated with the correct reset value
EVSYS	Updated Features with new event user verbiage Updated the CHSTATUS Register with a new Reset value for the USRRDY bitfield
SERCOM I²C	Updated the Signal Description with a cross reference to the proper I/O Multiplexing table In DMA, Interrupts and Events, erroneous information referring to the TX FIFO and RX FIFO was removed from table 28-1 and table 28-2 In Interrupts erroneous information regarding the RX FIFO and TX FIFO was removed Updated the SYNCBUSY Register to remove the SYSOP bitfield Updated the DATA Register with a new register Property and added a note to the DATA Bitfield
I²S	Added new slotsize information to PDM Reception.
TC	Updated the RCONT bit of the READREQ Register with new verbiage for clearing and reading the RREQ and RCONT bits.
USB	Updated the SPEED Bitfield of the STATUS Register with the proper allocation of low-speed and full-speed mode.
ADC	Updated the Block Diagram to properly display INTVCC0/1, and updated the note Updated the Note for the REFSEL bit of the REFCTRL Register
DAC	Updated the CTRLB Register with a new note for the REFSEL bitfield.
Electrical Characteristics at 85°C	In Maximum Clock Frequencies, table 37-7 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 37-24 37-25 37-26 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 37-32 37-34 37-35 Updated table 37-38 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
Electrical Characteristics at 105°C	In Maximum Clock Frequencies, table 38-4 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 38-10 38-11 38-12 Updated table 38-14 in Performance with the Hardware Offset and Gain Correction by applying the Conditions value to the whole column Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 38-15 38-16 38-17
Electrical Specifications at 125°C	In Maximum Clock Frequencies, table 39-4 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 39-13 39-14 39-15 39-16 39-17 39-18 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 39-19 39-20 39-22 39-23
AEC-Q100 125°C Specifications	In Maximum Clock Frequencies, table 40-7 and 40-9 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 40-24 40-25 40-26 40-27 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 40-30 40-32 40-33 Updated table 40-36 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
SAM DA1 Electrical Characteristics	In Maximum Clock Frequencies, table 41-6 was updated with a new maximum specification and units for the DAC input clock frequency The POR Operating Principle figure in Power-On Reset (POR) Characteristics was updated to properly display the RESET designation Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values and new rows added to the following tables: 41-23 41-24 41-25 Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells, add new parameter values, and notes to the following tables: 41-28 41-30 Updated table 41-32 in Bandgap and Internal 1.0V Reference Characteristics with new symbol values
Appendix B	Added a new Appendix for ISELED Specifications.
Packaging	The following packages were updated with new drawings: 64TQFP 64 pin QFN 64 Lead QFN with Sawn Wettable Flanks 64-ball UFBGA 48 pin TQFP 48 pin QFN 48 lead QFN with Sawn Wettable Flanks 45-ball WLCSP 32 pin TQFP 32 pin QFN 32 lead QFN with Sawn Wettable Flanks 35-ball WLCSP (Device Variant B) 35-ball WLCSP (Device Variant C) 35-ball WLCSP (Device Variant D)

SAM D21/DA1 Family

48.2 Revision G - April 2021