38.7.36 Tx Buffer Element Size Configuration

This register is write-restricted and only writable if bit fields CCCR.CCE bit (CCCR <1>) = 1 and CCCR.INIT bit (CCCR <0>) = 1.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.

Table 38-53. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: TXESC
Offset: 0xC8
Reset: 0x00000000
Property: Write-restricted

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      TBDS[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 2:0 – TBDS[2:0] Tx Buffer Data Field Size

In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS (TXESC <2:0>), the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes).
ValueNameDescription
0x0 DATA8 8 byte data field.
0x1 DATA12 12 byte data field.
0x2 DATA16 16 byte data field.
0x3 DATA20 20 byte data field.
0x4 DATA24 24 byte data field.
0x5 DATA32 32 byte data field.
0x6 DATA48 48 byte data field.
0x7 DATA64 64 byte data field.