38.7.12 Error Counter
Note: When CCCR.ASM bit (CCCR<2>)
is set, the CAN protocol controller does not increment TEC and REC when a CAN
protocol error is detected, but CEL is still incremented.
Table 38-29. Register Bit Attribute
Legend
| Symbol |
Description |
Symbol |
Description |
Symbol |
Description |
| R |
Readable bit |
HC |
Cleared by Hardware |
(Grey cell) |
Unimplemented |
| W |
Writable bit |
HS |
Set by Hardware |
X |
Bit is unknown at Reset |
| K |
Write to clear |
S |
Software settable bit |
— |
— |
| Name: | ECR |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | CEL[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | RP | REC[6:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TEC[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:16 – CEL[7:0] CAN Error
Logging
The counter is
incremented each time when a CAN protocol error causes the Transmit Error Counter or
Receive Error Counter to be incremented. It is reset by read access to CEL. The
counter stops at 0xFF; and the next increment of TEC or REC sets interrupt flag
IR.ELO bit (IR<22>).
Bit 15 – RP Receive Error
Passive
Bits 14:8 – REC[6:0] Receive Error
Counter
Actual state of the
Receive Error Counter, values between 0 and 127.
Bits 7:0 – TEC[7:0] Transmit Error
Counter
Actual state of the
Transmit Error Counter, values between 0 and 255.
