38.7.35 Tx FIFO/Queue Status

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indexes indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
Table 38-52. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: TXFQS
Offset: 0xC4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   TFQFTFQPI[4:0] 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
    TFGI[4:0] 
Access RRRRR 
Reset 00000 
Bit 76543210 
   TFFL[5:0] 
Access RRRRRR 
Reset 000000 

Bit 21 – TFQF Tx FIFO/Queue Full

ValueDescription
0 Tx FIFO/Queue not full.
1 Tx FIFO/Queue full.

Bits 20:16 – TFQPI[4:0] Tx FIFO/Queue Put Index

Tx FIFO/Queue write index pointer, range 0 to 31.

Bits 12:8 – TFGI[4:0] Tx FIFO/Queue Get Index

Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM bit (TXBC <30>) = ‘1’).

Bits 5:0 – TFFL[5:0] Tx FIFO Free Level

Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM bit (TXBC <30>) = ‘1’).