38.7.8 Timestamp Counter Configuration

This register is write-restricted and writable only if both CCCR.CCE bit (CCCR <1>) and CCCR.INIT bit (CCCR <0>) are set.
Table 38-25. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: TSCC
Offset: 0x20
Reset: 0x00000000
Property: Write-restricted

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     TCP[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       TSS[1:0] 
Access R/WR/W 
Reset 00 

Bits 19:16 – TCP[3:0] Timestamp Counter Prescaler

ValueDescription
0x0 - 0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Bits 1:0 – TSS[1:0] Timestamp Select

This field defines the timestamp counter selection.
ValueNameDescription
0x0 or 0x3 ZERO Timestamp counter value always 0x0000.
0x1 INC Timestamp counter value incremented by TCP.
0x2 - Reserved