30.3.18.3 Interrupt Enable Set Register

Table 30-27. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: INTENSET
Offset: 0x000C
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        FLTCAP 
Access R/W 
Reset 0 
Bit 15141312111098 
       CRCERRCRCDONE 
Access R/WR/W 
Reset 00 
Bit 76543210 
       DERRSERR 
Access R/WR/W 
Reset 00 

Bit 16 – FLTCAP ECC Fault Capture Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the ECC Fault Capture as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Bit 9 – CRCERR CRC Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the CRC Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Bit 8 – CRCDONE CRC Calculation Done Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the CRC Calculation Done as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Bit 1 – DERR ECC Double Error Detected Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the ECC Double Error Detected as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Bit 0 – SERR Single Error Corrected Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Flash SEC as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).