30.3.18.5 Debug Control Register

Table 30-29. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: DBGCTRL
Offset: 0x0018
Reset: 0x00000000
Property: PAC Write Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      DBGECC[1:0]CRCRUN 
Access R/WR/WR/W 
Reset 000 

Bits 2:1 – DBGECC[1:0] Debug ECC Mode

ECC errors from debugger reads are:

ValueDescription
x1 Not corrected, No Bus Error, INTLFAG is not updated, and FLT logic is not updated.
10 Corrected, Bus Error, INTFLAG is updated, and FLT logic operates as setup.
00 Corrected, No Bus ERR, INTFLAG is not updated, and FLT logic is not updated.

Bit 0 – CRCRUN CRC Debug Run

ValueDescription
0 CRC Logic Halts in Debug Mode
1 CRC Logic Runs in Debug Mode